There are two sets of PMC dedicated pins:
- 15 dedicated digital pins, DIO
- 4 dedicated analog pins, DIO_A
The DIO pins are on the bank_503 package bank. These pins provide functions such as boot mode selection, external reference clock input, power-on reset input, JTAG interface, status signals, error signals, and crystal oscillator pins for the real-time clock (RTC).
The DIO_A pins are on the bank_500 bank along with the digital PMC MIO bank 0 pins. The analog pins are for the system monitor voltage reference. The analog reference pins use the VCCO and ground for ESD protection only.
DIO Pins on Bank 503
The following table lists these dedicated digital I/O pins.
|DONE||Output||The DONE pin is an output-only, open-drain signal with a weak internal pull-up. An external pull-up is recommended. DONE is controlled by the DONE register. After POR, the DONE signal is Low. When the PLM successfully completes the boot sequence, the software sets the [DONE] bit High, which causes the output buffer to float and be pulled High externally.|
|ERROR_OUT||Output||The ERROR_OUT pin is an output-only, open-drain signal with a weak internal pull-up. An external pull-up is recommended. When an error occurs in the device, the ERROR_OUT signal is put in a High-Z state and pulled High. The specific errors that cause this pin to assert can be determined and programmed by software.|
|MODE[3:0]||Input||The MODE[3:0] pins are used to select the boot mode for the device. The value of these pins is captured on the rising edge of POR_B. See Boot Modes for available boot mode details.|
|POR_B||Input||The active-Low POR_B pin is the global power-on reset for the Versal ACAP. POR_B must remain asserted Low until power is fully applied to at least the VCC_PMC, VCCAUX_PMC, and VCCO_503. When the reset is released, the PMC begins the initialization and boot process.|
|PUDC_B||Input||The active-Low PUDC_B (pull-up during configuration) pin is used to select the behavior of the programmable logic (PL) I/O during configuration. If the PUDC_B pin is High, the PL I/O are put into 3-state mode. If the PUDC_B is Low, internal pull-ups at each programmable logic I/O are enabled. The PUDC_B pin does not affect the PS or PMC I/O during boot and configuration.|
|REF_CLK||Input||System reference clock pin. The system reference clock is required for all boot modes.|
|RTC_PADI||Input||RTC crystal input pin.|
|RTC_PADO||Output||RTC crystal output pin.|
|TCK||Input||JTAG test clock pin.|
|TDI||Input||JTAG test data input pin.|
|TDO||Output||JTAG test data output pin.|
|TMS||Input||JTAG test mode select pin|
DIO_A on Bank 500
The analog pins are used by the system monitor.
Note: The DIO_A pins and the PMC MIO bank 0 pins share the same package voltage bank, VCCO_500. However, the analog pins only use the VCCO_500 bank for ESD protection.
|Pin Name||Power Connection||Description|
|SYSMON_VREFN||Ground voltage reference||ADC reference voltage, negative (optional)|
|SYSMON_VREFP||Positive voltage reference||ADC reference voltage, positive|
|SYSMON_VN||Differential voltage||System monitor analog input, negative|
|SYSMON_VP||System monitor analog input, positive|