The raw error status 1 bits in the PMC_ERR1_STATUS register are listed in the following table.
| Error Name | System Error Status Reg Bit | JTAG Error Status Reg Bit | Description |
|---|---|---|---|
| reserved | 0 | 63 | reserved |
| BootROM NCR | 1 | 62 | BootROM non-correctable error; set during boot |
| PLM CR | 2 | 61 | PLM boot correctable error; set during boot |
| PLM NCR | 3 | 60 | PLM boot non-correctable error; set during boot |
| GSW CR | 4 | 59 | General software correctable error; set by any processor after boot |
| GSW NCR | 5 | 58 | General software non-correctable error; set by any processor after boot |
| CFU | 6 | 57 | CFU error |
| CFRAME | 7 | 56 | CFRAME error |
| PSM CR | 8 | 55 | PSM correctable error |
| PSM NCR | 9 | 54 | PSM non-correctable error |
| DDRMC MB CR | 10 | 53 | DDRMC MicroBlaze™ correctable ECC |
| DDRMC MB NCR | 11 | 52 | DDRMC MicroBlaze non-correctable ECC |
| NOC CR | 12 | 51 | NoC correctable error |
| NOC NCR | 13 | 50 | NoC non-correctable error |
| NOC user | 14 | 49 | NoC user error |
| MMCM lock | 15 | 48 | MMCM lock error |
| AIE CR | 16 | 47 | AI Engine correctable error |
| AIE NCR | 17 | 46 | AI Engine non-correctable error |
| DDRMC MC ECC CR | 18 | 45 | DDRMC memory correctable ECC |
| DDRMC MC ECC NCR | 19 | 44 | DDRMC memory non-correctable ECC |
| GT CR | 20 | 43 | GT correctable error |
| GT NCR | 21 | 42 | GT non-correctable error |
| SYSMON CR | 22 | 41 | System monitor correctable error |
| SYSMON NCR | 23 | 40 | System monitor non-correctable error |
| User PL0 | 24 | 39 | User-defined PL error |
| User PL1 | 25 | 38 | User-defined PL error |
| User PL2 | 26 | 37 | User-defined PL error |
| User PL3 | 27 | 36 | User-defined PL error |
| NPI Host | 28 | 35 | NPI Host reported error |
|
SSIT Error 3 |
29 |
34 |
Stacked silicon integrated (SSI) technology with super logic regions (SLR) errors 3 to 5 |