PMC Error Status 2

Versal ACAP Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2022-12-16
Revision
1.5 English

The raw error status 1 bits in the PMC_ERR2_STATUS register are listed in the following table.

Table 1. PMC System Error Accumulation Module Register 2
Error Name System Error Status Reg Bit JTAG Error Status Reg Bit Description
PMC APB 0 31 PMC APB programming interface address decode errors
PMC BootROM 1 30 BootROM validation error
RCU hardware 2 29 RCU hardware error
PPU hardware 3 28 PPU hardware error
PMC parity 4 27 PMC switch and IOP interconnect parity errors
PMC CR 5 26 PMC correctable errors
PMC NCR 6 25 PMC non-correctable errors
PMC SYSMON Alarms: 0 to 9

7
8
9
10
11
12
13
14
15
16

24
23
22
21
20
19
18
17
16
15

System monitor remote alarms for temperature shutdown and power supply failure
CFI NCR 17 14

CFI non-correctable error
SEU CRC 18 13 CFRAME SEU CRC error
SEU ECC 19 12 CFRAME SEU ECC error
reserved 20 11 reserved, returns 0
reserved 21 10 reserved, returns 1
RTC alarm 22 9 RTC alarm error
NPLL 23 8 PMC NPLL lock error; asserted while locking or when lock is lost
PPLL 24 7 PMC PPLL lock error; asserted while locking or when lock is lost
Clock monitor 25 6 Clock monitor errors
PMC timeout 26 5 PMC interconnect timeout errors; from mission and timeout interrupt status registers
PMC XMPU 27 4 PMC_XMPU error detection; includes read permission, write permission, and security violations
PMC XPPU 28 3 PMC XPPU error detection; includes SMID not found, SMID parity error, read permission, SMID access, and TrustZone violations

SSIT error 0
SSIT error 1
SSIT error 2

29
30
31

2
1
0

 Stacked silicon integrated (SSI) technology SLR errors 0 to 2