The PMC consists of control units and functional groups classified as blocks. The RCU and the PPU provide the central control and manage the PMC blocks.
ROM Code Unit
The RCU includes a MicroBlaze™ triple modular redundant system that exclusively executes the BootROM. The RCU is the first processing unit out of reset during boot and performs the device initialization, boot interface validation, and the loading of the platform loader and manager (PLM) into the PPU RAM. The RCU releases the PPU from reset and is responsible for PUF management.
Platform Processing Unit
The PPU includes a MicroBlaze triple modular redundant system that executes the platform loader and manager (PLM) software loaded into the PPU RAM by the RCU during hardware boot. The PLM is responsible for device boot and configuration and post-boot services. See Platform Processing Unit for more information.
The interconnect includes the main switch, the IOP switch, and other interconnects for the NPI and CFI programming interfaces. The RCU and PPU are masters on the main switch. The architecture allows PMC masters to access peripherals in the LPD. It can allow processors in other power domains to access PMC peripherals.
The PMC RAM is a 128 KB RAM that is used by the PLM. This is in addition to the 384 KB PPU RAM in the PPU.
The PMC I/O peripheral (IOP) block is a collection of peripheral controllers for initial boot and board control. The PMC IOP controllers on the PMC power domain include SD/eMMC, quad SPI, octal SPI, I2C, and two GPIOs. See the I/O Peripheral Controllers and the Flash Memory Controllers for more information.
The PMC integrated debug block includes the TAP controller, Arm DAP controller, and debug packet controller (DPC). This block supports basic device JTAG operations, ChipScope debug solution, Arm CoreSight trace and debug, and the high-speed debug solution. See Test and Debug for more information.
Run-time Service Request Registers
There are several sets of runtime service request registers. These are written to by system software to interrupt the platform loader and manager (PLM) running in the PPU processor.
System Error Accumulator
The system error accumulator enables system errors to generate an event. Events include asserting the ERROR_OUT pin, issuing a system or a POR, or asserting an interrupt to the PLM on PPU or the PSM firmware. See Error Accumulator Modules for more information.
The PMC is a general interrupt controller (GIC) proxy for system interrupts. The PMC and PSM global register module includes interrupt status and mask registers for the 150+ system interrupts. See System Interrupts for more information.
The PMC PPU uses the inter-processor interrupt (IPI) mechanism to send and receive interrupts from other processors; including the RPU, APU and PL-based processors. Each interrupt can include a short, 32 byte message. See Inter-Processor Interrupts for more information.
Resets and ClocksThe reset and clock functionality includes power-on reset and PLL-based clock sources. The PMC manages the clock hierarchy. At start-up, the reset controller ensures that the PMC (VCC_PMC, VCCAUX_PMC, VCCO_503) voltage rails are within their minimum operating range. The PMC clock controller provides programming registers for the PMC and NoC PLLs (PPLL, NPLL) and the clock generators for the reference clocks routed to the blocks. The PMC low-level reset functionality is described in Resets. Clocking is described in Clocks.
The RTC maintains an accurate time base for system and application software when the device is Off. The RTC has an alarm setting and can generate periodic interrupts to the PMC and other processors within the device. The RTC operates on the PMC auxiliary power domain when the device is On, or operates on the battery power domain when the device is off. The alarm feature can be used for user-level system services. See Real-Time Clock for more information.
The System Monitor (SYSMON) resides in the PMC and monitors operating conditions on the device. The SYSMON can access internal sensors for monitoring internal power supplies and temperature. MIO or high-density I/O (HDIO) pins can be used by the SYSMON for measuring voltage levels external to the device. The results captured by the SYSMON are stored in a register map that is accessible through platform management controller resources. See the Versal ACAP System Monitor Architecture Manual (AM006) for more information.
Device and Data Security
The PMC device and data security block supports secure boot and security management. This block includes the Xilinx hardware cryptographic accelerators, secure stream switch (SSS), the PMC DMAs, BBRAM controller, eFUSE controller, and the slave boot interface (SBI). Operations are described in Security Management . Functionality is described in Embedded Processor, Configuration, and Security Units .
The configuration block consists of the configuration frame unit (CFU) and the configuration frame interface (CFI) port. In addition to the PL configuration CFU interface, the integrated hardware is configured with AXI4 ports to the NoC and NPI.
The CFU is a bridge between the PMC main switch and the CFI, and handles the transfer of configuration data to the programmable logic configuration RAM (CRAM).
- I/O features
I/O Peripheral Controllers section
- I2C controller
- GPIO controller
Flash Memory Controllers section
- Quad SPI flash controller
- Octal SPI flash controller
- Two SD/eMMC flash controllers with delay-locked loop (DLL)
- 384 KB PPU RAM dedicated to the platform loader and manager (PLM)
- 128 KB PMC RAM dedicated to the PLM firmware
Clocks, Resets, and Power section
- PMC phase-locked loop (PPLL) generates the clock for flash interfaces and PMC controllers
- NoC phase-locked loop (NPLL) generates the clock for the network on chip (NoC) and PL fabric clocks
- Internal ring oscillator clock (PMC_IRO_CLK) provides the main clock to the PMC (clocks the RCU, PPU)
- Real-Time Clock (RTC) time keeping
Test and Debug section
- Debug packet controller (DPC) processes data packets for the high-speed debug port (HSDP) solution
- Single JTAG TAP controller supports boundary-scan, configuration and debug
- Single JTAG DAP controller supports Arm CoreSight trace and debug
- Security features and accelerators
- Xilinx memory protection unit (PMC_XMPU) for SBI and PMC RAM
- Xilinx peripheral protection units (PMC_XPPU) for I/O peripheral register modules, I/O peripheral memory space, and CFU
- Xilinx peripheral protection units (PMC_NPI_XPPU) for NPI programming interface
- Physical unclonable function (PUF) generates two device unique signatures per die. One signature is used for the key encryption key (KEK) and one signature is used as an identification value.
- Battery-backed RAM (BBRAM) supports security key storage
- eFUSE non-volatile memory supports security key storage
- DNA unique identifier provides product traceability
- True random number generator (TRNG) generates cryptographically strong random numbers
- RSA and elliptic curve digital signature algorithm (ECDSA) public-key cryptography enables authentication
- AES-GCM for symmetric key cryptography enables encryption and decryption
- SHA3-384 secure hash is used with the asymmetric algorithms to authenticate the programming device image