PMC Global Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The global registers serve several purposes.

  • Triple module redundant MicroBlaze™ processor controls, QoS for PPU on AXI
  • Storage registers (regular and persistent) and error storage for PLM firmware
  • Multiboot control
  • Mutex registers for processor software
  • Isolation and power supply storage
  • Power, isolation, reset, wake-up, and PL interrupt registers
  • DONE signal control, reset controls
  • Error management, firmware error storage registers
  • System error registers for PMC EAM
  • System interrupt registers
  • Soft error mitigation (SEM) in the PL configuration RAM (CRAM)

The platform service request registers allow system software to make power-up, power-down, isolation, and software reset requests by setting bits in the trigger registers.

The PMC global register set is accessed via a 32-bit APB programming interface that can be accessed by any permitted processor.

PMC Global Register Set

The following figure summarizes the entire PMC global register set.

Table 1. PMC Global Register Set
Register Name Access Type Description
Miscellaneous
GLOBAL_CTRL RW, R APB error, PLM firmware is loaded flag, MB status, and MB clock control (GLOBAL_CTRL).
PMC_MULTI_BOOT RW MultiBoot offset address is PMC_MULTI_BOOT[20:0]. For SD/eMMC1 boot modes, the partition type is PMC_MULTI_BOOT[31:28].
PPU_TMR_CTRL RW LMB ECC error propagation select.


            APB_MISC_ISR
        


            APB_MISC_IMR
        


            APB_MISC_IER
        


            APB_MISC_IDR
        

W1C APB address decode error, secure stream configuration error, and PUF access error.
32-bit Storage Registers


            GLOBAL_GEN_STORAGE0
        


            GLOBAL_GEN_STORAGE1
        


            GLOBAL_GEN_STORAGE2
        


            GLOBAL_GEN_STORAGE3
        


            GLOBAL_GEN_STORAGE4
        

RW Storage registers 0, 1, 2, 3, and 4 are reserved for use by the PLM firmware. There are also PSM_GLOBAL storage registers, see PSM Global Registers.


            PERS_GLOB_GEN_STORAGE0
        


            PERS_GLOB_GEN_STORAGE1
        


            PERS_GLOB_GEN_STORAGE2
        


            PERS_GLOB_GEN_STORAGE3
        


            PERS_GLOB_GEN_STORAGE4
        

RW

Persistent storage registers 0, 1, and 2 are reserved for use by PLM firmware. Persistent storage registers 3 and 4 are available for general use.
The persistent storage registers are only reset by an external POR.

PMC Software Service Errors
PMC_GSW_ERR RW General software service errors from PLM.
Power, Isolation, Reset, and Wake-up Requests
DOMAIN_ISO_STATUS R Isolation wall status.


            PWR_SUPPLY_STATUS
        

R Power supply status.


            REQ_PWRUP_ISR
        


            REQ_PWRUP_IMR
        


            REQ_PWRUP_IER
        


            REQ_PWRUP_IDR
        


            REQ_PWRUP_TRIG
        

R, W1C
R
W
W
W

System software power-up requests:
- LPD
- SoC power domain (SPD)
- PL
The SPD includes NoC and DDR memory controller power.


            REQ_PWRDWN_ISR
        


            REQ_PWRDWN_IMR
        


            REQ_PWRDWN_IER
        


            REQ_PWRDWN_IDR
        


            REQ_PWRDWN_TRIG
        

R, W1C
R
W
W
W

Power-down requests.


            REQ_ISO_ISR
        


            REQ_ISO_IMR
        


            REQ_ISO_IER
        


            REQ_ISO_IDR
        


            REQ_ISO_TRIG
        

R, W1C
R
W
W
W

Isolation requests.


            REQ_SWRST_ISR
        


            REQ_SWRST_IMR
        


            REQ_SWRST_IER
        


            REQ_SWRST_IDR
        


            REQ_SWRST_TRIG
        

R, W1C
R
W
W
W

System software reset requests:
- PS
- LPD
- SPD
- PL


            REQ_WAKEUP_ISR
        


            REQ_WAKEUP_IMR
        


            REQ_WAKEUP_IER
        


            REQ_WAKEUP_IDR
        


            REQ_WAKEUP_TRIG
        

R, W1C
R
W
W
W

CoreSight™ wake-up GPR for LPD and CPM.
Miscellaneous
DDR_RETENTION_CTRL RW Hold the XPIO output latched values to support DRAM self-refresh mode so the DDRMC power (SPD) can be shut down.
DBG_PWR_ACK RW CoreSight power-up acknowledge for LPD and CPM.
SSS_CFG RW Secure stream switch interface configuration.


            PPU_MB_FATAL
        


            PPU_MB1_FT_STATUS
        


            PPU_MB2_FT_STATUS
        


            PPU_MB3_FT_STATUS
        

R PPU TMR redundancy logic status.
PPU_RST RW PPU reset control.
PPU_RST_MODE RW PPU reset mode configuration.
PPU_AXI_QOS RW PPU AXI QoS value.
SAFETY_CHK RW Safety check register.
PL_STATUS R PL reset status.
DONE RW DONE output pin control.
PL-PS Signals
PMC_PL_GPO R See PL-PMC GPI and GPO Port Signals.


            PL_PMC_GPI_ISR
        

PL_PMC_GPI_IMR at 0x0914
PL_PMC_GPI_IER at 0x0918
PL_PMC_GPI_IDR at 0x091C
PL_PMC_GPI_ITR at 0x0920

R, W1C
R
W
W
W

Software Mutex Registers

32 Mutex registers:

            PMC_MUTEX_n
        

RW Software mutex registers.
Register Write Locks
PPU_RST_LOCK RW Control locking of PPU_RST resettable registers.
POR_LOCK RW Control locking of POR resettable registers.