PMC Global Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The global registers serve several purposes:

  • Register set control and status
  • Persistent and non-persistent 32-bit storage registers
  • Miscellaneous status, state, and errors
  • Platform service requests including power, isolation, reset, and wake-up
  • Safety check

The PMC global register set is accessed via a 32-bit APB programming interface that can be accessed by any permitted system processor.

The platform service request registers allow system software to make power-up, power-down, isolation, and software reset requests by setting bits in the trigger registers.

The entire PMC global register set is summarized in the following table.

Table 1. Versal ACAP PMC Global Register Set Overview
Register Name Offset Address Access Type Description
Miscellaneous
GLOBAL_CNTRL 0x0000 RW, R APB error, PLM firmware is loaded flag, MB status, and MB clock control (GLOBAL_CTRL)
PMC_MULTI_BOOT 0x0004 RW MultiBoot offset address is PMC_MULTI_BOOT[20:0]. For SD/eMMC1 boot modes, the partition type is PMC_MULTI_BOOT[31:28].
PPU_TMR_CTRL 0x0008 RW LMB ECC error propagation select


            APB_MISC_ISR
        


            APB_MISC_IMR
        


            APB_MISC_IER
        


            APB_MISC_IDR
        

0x0010+ W1C APB address decode error, secure stream configuration error, and PUF access error
32-bit Storage Registers


            GLOBAL_GEN_STORAGE0
        


            GLOBAL_GEN_STORAGE1
        


            GLOBAL_GEN_STORAGE2
        


            GLOBAL_GEN_STORAGE3
        


            GLOBAL_GEN_STORAGE4
        

0x0030+ RW Storage registers 0, 1, 2, 3, and 4 are reserved for use by the PLM firmware. There are also PSM_GLOBAL storage registers, see PSM Global Registers.


            PERS_GLOB_GEN_STORAGE0
        


            PERS_GLOB_GEN_STORAGE1
        


            PERS_GLOB_GEN_STORAGE2
        


            PERS_GLOB_GEN_STORAGE3
        


            PERS_GLOB_GEN_STORAGE4
        

0x0050+ RW

Persistent storage registers 0, 1, and 2 are reserved for use by PLM firmware. Persistent storage registers 3 and 4 are available for general use.
The persistent storage registers are only reset by an external POR.

PMC Software Service Errors
PMC_GSW_ERR 0x0064 RW General software service errors from PLM
Power, Isolation, Reset, and Wake-up Requests
DOMAIN_ISO_STATUS 0x0100 R Isolation wall status


            PWR_SUPPLY_STATUS
        

0x010C R Power supply status


            REQ_PWRUP_ISR
        


            REQ_PWRUP_IMR
        


            REQ_PWRUP_IER
        


            REQ_PWRUP_IDR
        


            REQ_PWRUP_TRIG
        

0x0110+

R, W1C
R
W
W
W

System software power down requests:
- LPD
- SoC power domain (SPD)
- PL
The SPD includes NoC and DDR memory controller power


            REQ_PWRDWN_ISR
        


            REQ_PWRDWN_IMR
        


            REQ_PWRDWN_IER
        


            REQ_PWRDWN_IDR
        


            REQ_PWRDWN_TRIG
        

0x0210+

R, W1C
R
W
W
W

Power-up requests


            REQ_ISO_ISR
        


            REQ_ISO_IMR
        


            REQ_ISO_IER
        


            REQ_ISO_IDR
        


            REQ_ISO_TRIG
        

0x0310+

R, W1C
R
W
W
W

Isolation requests


            REQ_SWRST_ISR
        


            REQ_SWRST_IMR
        


            REQ_SWRST_IER
        


            REQ_SWRST_IDR
        


            REQ_SWRST_TRIG
        

0x0410+

R, W1C
R
W
W
W

System software reset requests:
- PS
- LPD
- SPD
- PL


            REQ_WAKEUP_ISR
        


            REQ_WAKEUP_IMR
        


            REQ_WAKEUP_IER
        


            REQ_WAKEUP_IDR
        


            REQ_WAKEUP_TRIG
        

0x0430+

R, W1C
R
W
W
W

CoreSightâ„¢ wake-up GPR for LPD and CPM
Miscellaneous
DDR_RETENTION_CTRL 0x0324 RW Hold the XPIO output latched values to support DRAM self-refresh mode so the DDRMC power (SPD) can be shut down
DBG_PWR_ACK 0x0444 RW CoreSight power-up acknowledge for LPD and CPM
SSS_CFG 0x0500 RW Secure stream switch interface configuration


            PPU_MB_FATAL
        


            PPU_MB1_FT_STATUS
        


            PPU_MB2_FT_STATUS
        


            PPU_MB3_FT_STATUS
        

0x0610
0x0614
0x0618
0x061C

R PPU TMR redundancy logic status
PPU_RST 0x0620 RW PPU reset control
PPU_RST_MODE 0x0624 RW PPU reset mode configuration
PPU_AXI_QOS 0x0634 RW PPU AXI QoS value
SAFETY_CHK 0x0800 RW Safety check register
PL_STATUS 0x0880 R PL reset status
DONE 0x0884 RW DONE output pin control
PL-PS Signals
PMC_PL_GPO 0x0900 R See PL-PMC GPI and GPO Port Signals


            PL_PMC_GPI_ISR
        

PL_PMC_GPI_IMR at 0x0914
PL_PMC_GPI_IER at 0x0918
PL_PMC_GPI_IDR at 0x091C
PL_PMC_GPI_ITR at 0x0920

0x0910+

R, W1C
R
W
W
W

SEM


            SEM_STATUS
        


            SEM_ERROR
        

0x1018
0x1020

RW SEM CRAM and NPI scan status
SEM_CFR_ERRCODE 0x1020 RW CRAM scan errorc code (or SEM_CMD_REG0)


            SEM_CRAMERR_ADDRL0
        


            SEM_CRAMERR_ADDRH0
        

(4 addresses: 0 to 3)

0x1040+ RW Four error addresses, eight registers
Software Mutex Registers

32 Mutex registers:

            PMC_MUTEX_n
        

0x1100+ RW Software mutex registers
Register Write Locks
PPU_RST_LOCK 0x1200 RW Control locking of PPU_RST resettable registers
POR_LOCK 0x1204 RW Control locking of POR resettable registers