The PMC interconnect includes two large AXI switches with several memory protection units. The PMC also includes an AXI4-Stream switch with channels the SBI, DMA, AES, and SHA3. The DPC and JTAG integrated debug include several different interfaces and special-use channels.
The PMC interconnect includes the following switches:
- PMC main switch, including the Aux and APB switches
- PMC IOP switch
Memory Protection Units
The PMC interconnect provides access to protection units for the following:
- Xilinx memory protection unit (XMPU) for the PMC_RAM
- XPPU_NPI controller dedicated to the NPI host bus controller
- XPPU controller used for the PMC peripheral interfaces
For more information, see Xilinx Memory Protection Unit and Xilinx Peripheral Protection Unit.
Secure Stream Switch
Secure stream switch (SSS) is based on the AXI4-Stream protocol.
- Links security accelerators, SBI, and PMC DMAs
- SBI enables the JTAG or SelectMAP interface
- AXI 128-bit interface link to the PS and the NoC, with conversion of the NoC protocol handled outside of the PMC
- AXI 32-bit controller port that links to the NPI host controller for the NPI programming interfaces
Configuration Frame Interface
Configuration frame interface (CFI) is a dedicated high-bandwidth 128-bit bus to the PL.
The PMC interconnect is shown in the following figure.
Figure 1. PMC Interconnect Block Diagram