- Full-power domain (FPD) functional units and interconnect
- Low-power domain (LPD) functional units and interconnect
- Platform management controller (PMC) functional units and interconnect
- DDR memory controller, programmable logic (PL)
Integrated Peripheral Options
- Ethernet, crypto, Interlaken
Integrated Hardware Options
- AI Engine, XRAM, CPM
Processing System (RPU and APU)
The PS includes two Arm® Cortex®-R5F RPU processors and two Arm Cortex-A72 APU processors. These provide programmers with real-time and application operating environments.
The RPU is in the LPD and the APU is in the FPD.
Platform Management Controller
The system starts up and is controlled by the PMC. The ROM code unit (RCU) boots the hardware and loads the initial platform loader and manager (PLM) firmware into the PPU processor. The PMC is in its own power domain. The boot sequences and platform control functions are described in Platform Boot, Control, and Status.
The integrated hardware is configured with programmable device image (PDI) files. The PDIs are composed of configuration data object (CDO) files and other elements that are processed by the PLM. This includes configuring the PS, NoC, DDR memory controller, and others. These files are described in the Versal ACAP System Software Developers Guide (UG1304).
There are many integrated component and peripheral options in the Versal ACAP that are summarized in the Versal Architecture and Product Data Sheet: Overview (DS950) based on device series and device within a series. A high-level summary of all the functional units is include in the TRM in the Processing System section.