The PMC start-up begins with the release of the POR_B reset pin. The reset pin must be held asserted for at least the TPORB time after the critical power supplies have reached their operating level. This is defined to be 10 μs in the Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956) and the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).
Power Supplies Required
The minimum power supplies required for boot depends on the boot device selected by the boot mode pins. For JTAG boot, these three power supplies are required:
- VCCO_503 I/O (see PMC Dedicated Pins)
These three power supplies must be maintained to keep the device from generating an external POR.
When a boot device is selected on an MIO bank, the bank power supply must also be valid:
- VCCO_500 or VCCO_501 (PMC MIO pin banks 0 and 1)
The four power supplies are sufficient to boot from a device and load a PLM firmware image into the PPU processor.
Additional Power Supplies
All power supplies are listed in the Power Pins section. Some power domains require other power domains to be on as well. The dependencies of one power domain on another power domain are described in the Power chapter.
Alternate Boot Mode Selection
The release of the POR causes the hardware to capture the state of the boot mode pins and store the value in the BOOT_MODE_POR register and the BOOT_MODE_USER [Boot_Mode] bit field. The BOOT_MODE_USER register enables software to select a different boot mode by setting the [use_alt] bit to 1 and writing the 4-bit boot mode code into the [alt_boot_mode] field.
For the initial phases, the PMC hardware checks are performed and the RCU is released to execute the BootROM. The primary task of the RCU is to fetch the boot header from the boot device. This header provides important boot information about the start-up.
After the RCU has performed its housekeeping duties, it sets up the boot interface and initializes the required registers. The RCU then loads the platform loader and manager (PLM) firmware into the PPU RAM memory and releases the PPU processor from reset. Next, the PPU begins to execute the PLM firmware that reads the program device image from the boot source.