PS FPD Architecture

Versal ACAP Technical Reference Manual (AM011)

Document ID
Release Date
1.5 English

The FPD includes the Cortex-A72 application processor MPCore (APU) with an L2 cache attached to a Cache Coherent Interconnect (CCI). The transactions originating outside of the APU can be routed to the system memory management unit (SMMU) to allow them access to APU shared memory and the APU L2-cache.