The FPD includes several functional units:
- Application processing unit (APU)
- GIC-500 generic interrupt controller
- System memory management unit (SMMU)
- CCI-500 cache coherent interconnect
Application Processing Unit
The application processing unit (APU) is based on a dual-core Arm® Cortex®-A72 processors with the system memory management unit (SMMU), cache coherent interconnect (CCI) unit, interconnect channels to the rest of the system, and system peripherals. The SMMU and CCI work together to provide a shared memory environment between the PS, PMC, and PL processors that can be tied to the APU 1 MB L2 cache. See the Application Processing Unit chapter for more information.
The APU processors can be used for computations, control-plane applications, operating systems, communications interfaces, and more. The TRM describes the architecture and the programming model for the APU functional units. Linux and bare-metal software stacks execute in the APU and RPU in a homogeneous or a heterogeneous environment. The APU software environment is described in the Versal ACAP System Software Developers Guide (UG1304).
GIC Interrupt Controller
To manage system interrupts, the APU includes the GIC interrupt controller, which is based on the Arm GIC-500 generic interrupt controller and is compatible with the Arm GIC v3 architecture. See the GIC-500 Interrupt Controller section for more information.
System Memory Management Unit
The System Memory Management Unit (SMMU) translates 48-bit virtual addresses into 44-bit physical addresses. It has 7 individual table buffer units (TBU) that is managed by one translation control unit (TCU).
Cache Coherent Interconnect
The Versal device includes an APU L2-cache that is accessible by routing transactions through the SMMU for translation to a physical address for the Cache Coherent Interconnect (CCI).
System watchdog timer (SWDT) for healthy and secure software (System Watchdog Timers).