PS LPD Architecture

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

The PS low-power domain (LPD) includes the Cortex-R5F MPCore processors with their tightly-coupled memories (TCM), OCM memory, I/O peripherals (IOP), and the PSM controller for PS power control. The RPU also has a direct interconnect to the accelerator RAM (XRAM, if present) that can be partitioned and shared with logic in the PL.