The low-power domain (LPD) includes several functional units:
- RPU: Arm-based dual Cortex-R5F processor cores
- PL-390 generic interrupt controller
- Tightly-coupled memories
- OCM switch and memory
Real-time Processing Unit
The real-time processing unit (RPU) is based on a dual-core Arm Cortex-R5F processor with L1 caches and tightly-coupled memories (TCMs) that are dedicated to the RPU cores. The CPUs feature out-of-order execution that is coupled with a single/double precision floating point unit (FPU). The processor also includes a general interrupt controller (GIC PL-390) to receive system interrupts.
The RPU can be configured into a dual-processor mode for greatest performance or into a lock-step mode for greatest safety. Each processor core includes L1 instruction and data caches and three banks of TCMs. The RPU can provide deterministic execution times for real-time applications by operating out of the TCM memory.
The TRM describes the architecture and the programming model for the controllers and other functional units. Linux and bare-metal software stacks execute in the APU and RPU in a homogeneous or a heterogeneous environment. Software environments within the APU can be partitioned on a hardware basis.
The RPU is described in the Real-time Processing Unit chapter. The software programming environment is described in the Versal ACAP System Software Developers Guide (UG1304).
Each Cortex-R5F core includes:
- 32 KB L1 instruction cache with ECC
- 32 KB L1 data cache with ECC
- FPU: single and double precision
- Embedded trace microcell (ETM) to support real-time debug and trace; ETM communicates with the Arm CoreSight™ debug system
Each RPU processor can be individually configured for inter-processor interrupts (IPI). The RPU processors have a common power island. The TCMs are divided into four banks with four power island controls. However, all power islands must be enabled to access any of the TCMs.
The RPU is documented in Real-time Processing Unit chapter.
PL-390 Generic Interrupt Controller
See Arm Documents.
The RPU TCMs provide a deterministic, low-latency memory space for the RPU. There are multiple memory banks. The TCM banks are protected by ECC. Accesses to the TCMs are not cached.
The distribution of TCM depends on the processor mode:
- Single cycle read access with ECC protection
- Dual-processor, performance mode: each processor has 128 KB of TCM
- Lock-step, safety mode: TCMs are combined for a total of 256 KB of memory
The TCMs are described in Tightly-coupled Memories.
OCM Switch with OCM and XRAM Memory
The OCM switch is optimized to service RPU and APU requests directed to the OCM and accelerator RAM (XRAM) memories.