There are two configurable PS to PL AXI interfaces. One is from the FPD to the PL (via the LPD). The other is from the LPD to the PS. The interface parameters and the PS-to-PL AXI interface attributes are listed in the following table.
The two PS to PL interfaces are mapped within the low 4 GB memory address space.
|Interface Name||Alternate Name||Address Width (Bits)||Data Width (Bits)||Base Address||Size||Notes|
|FPD_AXI_PL||M_AXI_FPD, AFIFS||44||32, 64, or 128||
|FPD_ADDR_PL||PLAT||48||None||N/A||N/A||Address translation only|
|LPD_AXI_PL||M_AXI_LPD, AFIFS||44||32, 64, or 128||
Note: The data bus width of the LPD_AXI_PL and FPD_AXI_PL interfaces are controlled by the LPD_AXI_PL_Width and FPD_AXI_PL_Width registers, respectively.