PS to PL Interfaces

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are two configurable PS to PL AXI interfaces. One is from the FPD to the PL (via the LPD). The other is from the LPD to the PS. The interface parameters and the PS-to-PL AXI interface attributes are listed in the following table.

The two PS to PL interfaces are mapped within the low 4 GB memory address space.

Table 1. PS-to-PL AXI Interfaces
Interface Name Alternate Name Address Width (Bits) Data Width (Bits) Base Address Size Notes
From FPD
FPD_AXI_PL M_AXI_FPD, AFIFS 44 32, 64, or 128 0x8000_0000 512 MB  
FPD_ADDR_PL PLAT 48 None N/A N/A Address translation only
From LPD
LPD_AXI_PL M_AXI_LPD, AFIFS 44 32, 64, or 128 0xA400_0000 192 MB  
0xB000_0000 256 MB  
Note: The data bus width of the LPD_AXI_PL and FPD_AXI_PL interfaces are controlled by the LPD_AXI_PL_Width and FPD_AXI_PL_Width registers, respectively.