The raw error status 1 bits in the PSM_ERR1_STATUS register are listed in the following table.
| Error Name | System Error Reg Bit | Description |
|---|---|---|
| PS_SW_CR | 0 | PS software write can set this bit |
| PS_SW_NCR | 1 | PS software write can set this bit |
| PSM_B_CR | 2 | PSM firmware write can set this bit |
| PSM_B_NCR | 3 | PSM firmware write can set this bit |
| MB_FATAL | 4 | OR of MicroBlaze fatal errors |
| PSM_CR | 5 | PSM correctable error |
| PSM_NCR | 6 | PSM non-correctable error |
| OCM_ECC | 7 | OCM ECC non-correctable error |
| L2_ECC | 8 | APU L2-cache ECC non-correctable error |
| RPU_ECC | 9 | OR of many errors |
| RPU_LS | 10 | |
| RPU_CCF | 11 | |
| GIC_AXI | 12 | APU GIC access port |
| GIC_ECC | 13 | APU GIC ECC non-correctable error |
| APLL_LOCK | 14 | APU PLL lock error; asserted while locking or when looses lock |
| RPLL_LOCK | 15 | RPU RPLL lock error; asserted while locking or when looses lock |
| CPM_CR | 16 | CPM correctable error |
| CPM_NCR | 17 | CPM non-correctable error |
| LPD_APB | 18 | LPD APB address decode errors: IPI, USB_2, CRL, S_AXI_LPD. LPD_IOP_SLCR, LPD_IOP_SECURE_SLCR |
| FPD_APB | 19 | FPD APB address decode errors: CRF, S_AXI_HP, S_AXI_HPC. FPD_SLCR, FPD_SECURE_SLCR |
| LPD_PAR | 20 | LPD AXI main interconnect parity error |
| FPD_PAR | 21 | FPD AXI main interconnect parity error |
| IOP_PAR | 22 | LPD IOP interconnect parity error |
| PSM_PAR | 23 | PSM interconnect parity error |
| LPD_TO | 24 | LPD interconnect timeout error |
| FPD_TO | 25 | FPD interconnect timeout error |
| PSM_TO | 26 | PSM interconnect timeout error |
| XRAM_CR | 27 | Accelerator RAM correctable error |
| XRAM_NCR | 28 | Accelerator RAM non-correctable error |
| reserved | 29 to 31 | reserved |