PSM Local Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The PS power island control and status registers are listed in the following table.

Table 1. PS Power Island Control and Status Registers
Register Name Offset Address Access Type Description


            APU0_PWR_CTRL
        


            APU0_PWR_STATUS
        


            APU1_PWR_CTRL
        


            APU1_PWR_STATUS
        

0x0000+

RW
R
W
R

APU cores power control and status


            RPU_PWR_CTRL
        


            RPU_PWR_STATUS
        

0x0080
0x0084

RW
R

RPU power control and status


            L2_PWR_CTRL
        


            L2_CE_CTRL
        


            L2_PWR_STATUS
        

0x00B0
0x00B8
0x00BC

RW
RW
R

L2 cache power control/status and chip enables


            OCM_PWR_CTRL
        


            OCM_CE_CTRL
        


            OCM_PWR_STATUS
        

0x00C0
0x00C8
0x00CC

RW
RW
R

OCM power control/status and chip enables


            TCM_PWR_CTRL
        


            TCM_CE_CTRL
        


            TCM_PWR_STATUS
        

0x00D0
0x00D8
0x00DC

RW
RW
R

RPU power control/status and chip enables


            GEM_PWR_CTRL
        


            GEM_CE_CTRL
        


            GEM_PWR_STATUS
        

0x00E0
0x00E4
0x00E8

RW
RW
R

GEM power control/status and chip enables


            DOMAIN_ISO_CTRL
        

0x00F0 RW Isolations: LPD-FPD and LPD-XRAM


            LOC_PWR_STATE
        

0x0100 RW Power status of LPD blocks


            APB_ERR_ISR
        


            APB_ERR_IMR
        


            APB_ERR_IER
        


            APB_ERR_IDR
        

0x0320

R, W1C
R
W
W

APB address decode error interrupt


            APU_WFI_STATUS
        

0x0418 R APU wake for status on APU cores and L2 cache