The system starts up and is controlled by the PMC. The ROM code unit (RCU) boots the hardware and loads the initial platform loader and manager (PLM) firmware into the PPU processor. The boot sequences and platform control functions are described in Platform Boot, Control, and Status.
The integrated hardware is configured with programmable device image (PDI) files. The PDIs are composed of configuration data object (CDO) files and other elements that are processed by the PLM. This includes configuring the PS, NoC, DDR memory controller, and others. These files are described in the Versal Adaptive SoC System Software Developers Guide (UG1304).
The PMC operations are divided into four phases beginning with a hardware reset that will start or restart the ROM code unit (RCU) executing its BootROM code. After reset, the RCU configures the system to access the boot device to find and process the boot header. The RCU downloads the platform loader and manager (PLM) firmware from the boot device and writes it into the PPU processor memory.
The PLM loads PSM firmware into the processing system manager (PSM) memory to manage the PS.
When the RCU finishes with the device boot, the PLM takes control of the system for further configuration and to load system software for the RPU, APU, and processors in the programmable logic.
- Pre-boot (phase 1): power-up and reset (PMC hardware)
- Boot setup (phase 2): initialization and boot header processing (RCU BootROM code)
- Load platform (phase 3): boot image processing and device configuration (PPU PLM firmware)
- Post-boot (phase 4): platform management and monitoring services (RCU and PLM)
During normal runtime, the PLM and the PSM firmware monitor and respond to system requests and events. The PMC is in all devices and is required for all operating modes.
- Hardware reset control circuits and sequencers
- Initialization of the device after a power-on reset (POR) and system reset (SRST) by the RCU BootROM
- Boot and configuration from a supported boot device
- Configure the adaptable engines in the PL using the configuration frame interface (CFI)
- Performs security core functions that supports encryption and decryption, authentication, and key management
- Provides test and debug infrastructure to support boundary-scan and Arm CoreSight trace and debug
- Monitors system activity and responds to security and functional safety events
- Releases the PS from reset
- Controls system power
- Manages system errors
Additional information is in the Platform Management chapter.