The PMC operations are divided into four phases beginning with hardware resets that start or restart the ROM code unit (RCU). After reset, the RCU executes the BootROM to configure the system to access the boot device and process the boot header. The RCU downloads the platform loader and monitor (PLM) firmware from the boot device and writes it into the PPU memory. It can also load firmware into the processing system manager (PSM) memory. When the RCU finishes with the device boot, the PLM takes control of the system for further configuration and, optionally, loads system software for the RPU, APU, and other processors.
During normal runtime, the PLM works with other parts of the PMC and the PSM firmware to monitor and respond to system requests and events. The PMC is in all devices and is required in all operating modes.
- Hardware reset control circuits and sequencers
- Initialization of the device after a power-on reset (POR) and system reset (SRST) by the RCU BootROM
- Boot and configuration from a supported boot device
- Configure the adaptable engines using the configuration frame interface (CFI)
- Performs security core functions that supports encryption and decryption, authentication, and key management
- Provides test and debug infrastructure to support boundary-scan and Arm CoreSight trace and debug
- Monitors system activity and responds to security and functional safety events
- Releases the PS from reset and provides system power and error management services
The Versal ACAP Technical Reference Manual (AM011), together with the Versal ACAP Register Reference (AM012) describe the details of what can be configured, controlled, and monitored in the PMC.
The TRM includes several PMC-related content areas:
- Section II, Hardware Architecture
- Basic PMC hardware functionality and architecture are described in the PMC Architecture chapter.
- Section III, Platform Boot, Control, and Status
- The progression of activity from reset to device boot to platform management is described in the dedicated Platform Boot, Control, and Status section.
- Section VII, Embedded Processor, Configuration, and Security
- The detailed descriptions of the PMC-centric functional units are located in the Embedded Processor, Configuration, and Security Units section.
- Section XIII Flash Memory Controllers
- All flash memory controllers can optionally be used as a primary boot interface. The general functionality of the flash memory controllers is described in the Flash Memory Controllers TRM section. The boot devices and flows are described in the Boot Modes chapter.
- System-level Functionality Sections
- The Test and Debug TRM section describes the details of the JTAG and CoreSight debug hardware.
- The clock and reset controllers are described in the Clocks, Resets, and Power TRM section. Also included in this section is the power architecture of the Versal ACAP.