Power

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The device power architecture includes power domains and PS-based power islands. The power domains are large areas of the device that have their own set of power pins. The power islands are smaller areas within the LPD and FPD power domains. The power island are controlled by onboard power FETs. These FETs are controlled by register bits. The power domains and islands are shown in the Power Diagram.

The power domain states and the transitions from one state to another have some restrictions. For the power domains and the power islands, the interconnect traffic must be brought to a halt before power-down. The PS power islands are controlled by the PSM controller in the LPD. The power-up process includes sequencing of power, clocks, and resets.

Power management is described in Power Management.

Power Domains

  • PMC power domain: platform management controller and functional units
  • LPD (low-power domain):
    • RPU MPCore processor
    • LPD functional units
    • CPM5, if present
  • FPD (full-power domain): application processing unit and functional units
  • PL power domain
    • PL building blocks and clock structures; the count is device dependent
    • CPM4, if present
    • AI Engine, if present
  • SPD (system power domain)
    • NoC and NPI interconnect
    • DDR memory controllers
  • BPD (battery power domain)
    • Real-time clock (RTC)
    • Battery-backed RAM (BBRAM)
  • Gigabit transceivers for high-speed I/O (GTM, GTY, GTYP)
    • AVCC, AVCCUAX, AVTT, AVTTRCAL transceiver pins

Power Islands

The LPD and FPD processors and some subsystem units are on their own power islands. These are controlled by the PSM.

  • RPU processor (all cores together)
  • APU cores (individually)
  • APU L2-cache
  • 4 MB XRAM supports a total of 16 power islands (1 per 256 KB sub-bank)

The power island controls and service request registers are listed in Power Islands.

Power Reduction Features

There are several power reduction features. In addition to power control, the processors have sleep modes. The power domains are controlled by output pins attached to external power supplies. The PS power islands are controlled by on-chip power FETs that are controlled by registers accessible to the PSM.

  • Processor sleep/wake feature
  • PS and PL clock frequency reduction and clock gating
Note: PL clocks can enabled and disabled by system software using an EMIO signal from one of the GPIO controllers.