Power Control and Status

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The persistent control and status registers are summarized in the following table.

Table 1. Persistent Power Control and Status Registers
Register Offset Address Description
PSM_LOCAL Power Control and Status Registers


            APU0_PWR_CTRL
        


            APU1_PWR_CTRL
        


            L2_PWR_CTRL
        


            L2_CE_CTRL
        

0x0000
0x0004
0x00B0
0x00B8

APU and L2 cache power control and status.


            RPU_PWR_CTRL
        


            RPU_PWR_STATUS
        


            TCM_PWR_CTRL
        


            TCM_CE_CTRL
        

0x0080
0x0084
0x00B0
0x00B8

RPU and TCM power control and status.


            OCM_PWR_CTRL
        


            OCM_CE_CTRL
        


            OCM_PWR_STATUS
        

0x00C0
0x00C8
0x00CC

OCM power island control and status, and chip enable control.


            GEM_PWR_CTRL
        


            GEM_CE_CTRL
        


            GEM_PWR_STATUS
        

0x00E0
0x00E4
0x00E8

GEM power island control, status and chip enable control.
DOMAIN_ISO_CTRL 0x00F0 Isolation control for LPD-FPD and XRAM boundaries.


            LOC_PWR_STATE
        


            LOC_AUX_PWR_STATE
        

0x0100
0x0104

Power-up status for all islands within the PS.