The power pins include major power domains for the logic, the small circuits for analog and digital circuits, and the power for I/O blocks.
The power domain inter-dependencies are described in the Power chapter, including how the power pins connect to the power domains as shown in the Power Diagram section.
The power pin specifications are provided in the data sheets listed in References.
Power Design Tools
For current designs with the Versal device, see the Xilinx Power Estimator (XPE) design tool for estimating power consumption and providing power sequence and thermal information.
For more information about power design, see https://www.xilinx.com/power.
The power pins are listed in the following table.
|Pin Name||Power Supply Description|
|Platform Management Controller|
|VCC_BATT||Battery-backed power domain. When VCC_BATT is not used, connect to ground.|
|VCC_FUSE||eFUSE programming. Ideally VCC_FUSE should only be powered up when eFUSE programming is being done. If not programming eFUSE in the field, VCC_FUSE should be connected to ground.|
|VCC_PMC||PMC power domain|
|VCCAUX_PMC||Auxiliary for the PMC|
|VCCAUX_SMON||Analog for the ADC and other analog circuits in the system monitor|
|VCCO_500||PMC MIO bank 0 with dedicated analog signals DIO_A|
|VCCO_501||PMC MIO bank 1|
|VCCO_503||PMC dedicated I/O (DIO) bank|
|VCC_PSFP||PS full-power domain (FPD)|
|VCC_PSLP||PS low-power domain (LPD)|
|VCCO_502||LPD MIO bank PS (bank 502)|
|VCC_RAM||Block RAM, UltraRAM, and PL clocking network|
|VCC_SOC||NoC, NPI, and DDRMC SoC power domain (SPD)|
|VCCINT||Internal logic (programmable logic, integrated hardware|
|VCCO_[bank number]||HDIO LVCMOS output drivers (per bank)|
|GTx_AVCC||Gigabit transceiver; analog internal circuits|
|GTx_AVCCAUX||Gigabit transceiver; auxiliary analog transceivers|
|GTx_AVTT||Gigabit transceiver; analog transmit driver|
|GTx_AVTTRCAL||Gigabit transceiver; analog resistor calibration|