Processor Control and Status Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The following tables provide an overview of the AArch32 registers and the APU core private counters. The MPCore timers are defined by the AArch64 architecture specification.

Local Register Access

The CNTPCT register holds the current physical counter value. The CNTPCT counter operates in the LPD power domain to provide a reliable and uniform view of the system time to each of the APU cores. This counter is controlled by the TIMESTAMP_REF_CTRL register.

Table 1. AArch32 Register Overview
Function Control Register
Timer frequency CNTFRQ
Kernel control CNTKCTL
Hypervisor control CNTHCTL
Virtual offset CNTVOFF
Table 2. APU Core Private Counter (AArch64)
Counter - Timer Physical Counter Virtual Counter Physical Secure Counter Hypervisor Physical Counter
Timer value CNTP_TVAL_EL0 CNTV_TVAL_EL0 CNTPS_TVAL_EL1 CNTHP_TVAL_EL2
Timer control CNTP_CTL_EL0 CNTV_CTL_EL0 CNTPS_CTL_EL1 CNTHP_CTL_EL2
Compare value CNTP_CVAL_EL0 CNTV_CVAL_EL0 CNTPS_CVAL_EL1 CNTHP_CVAL_EL2
Timer count CNTPCT_EL0 CNTVCT_EL0