Programmable Logic Overview

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The programmable logic (PL) is a scalable structure that provides the ability to create many possible functions. The PL logic regions include building blocks and interfaces to NoC, I/O pins, and in some cases the processing system. These can be configured together to create almost any type of hardware functionality including hardware accelerators, microprocessors, functional pipeline units, and most types of peripherals.

The dynamically programmable logic complements the functionality of the processing system and integrated hardware to improve application performance. The PL instantiates system functionality and provides connectivity between the system and integrated hardware and peripherals.

The PL includes several Integrated Peripheral Options for many different high-performance I/Os.

PL Configuration

The connections and configuration of the PL elements are captured in the AMD Vivado™ design suite and the AMD Vitis™ unified software platform tool chain using a programmable device image (PDI). The PDI contains PL configuration frames (CFRAME), which are sent by the PLM to the configuration frame unit (CFU) for processing. The CFU interfaces to the PL via the configuration frame interface (CFI). The PL can be configured during the boot process and can be reconfigured during normal system operation. The PL configuration can be read-back for debug and functional safety applications. The CFU is described in Configuration Frame Unit and the CFI is described in Configuration Frame Interface.

Building Blocks

The PL building blocks include the DSP Engine, configurable logic block (CLB), block RAM, and UltraRAM integrated components. These components are surrounded by clocking structures and wiring pathways. The PL makes connections between the PS, CPM, PMC, NoC, AI Engine, GTs, XPIO banks for DDRMC/PL, LVCMOS high-density I/O (HDIO) buffers, and components instantiated within the PL.

The PL building blocks include:

  • DSP Engine (intelligent)
  • CLB (adaptable)
  • Block RAM and UltraRAM (adaptable)

Tool Support

The AMD Vivado™ /AMD Vitis™ development system provides a large library of complex functional components (microprocessors, peripherals, filters, etc.) that can be instantiated and connected to create a design. Additionally, a hardware description language can be used to describe specific functions in the design. The design tools then translate the design into the building blocks of the PL. The PL can be partially or fully programmed during the boot start-up and as a service operation when the system is operating.