Programming Model

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

The resets are managed by the PLM and PSM firmware. The PLM firmware manages the power and resets at the device level and for the PMC, NoC, DDRMC, and integrated hardware subsystems. The PSM manages the power and resets of the PS, which includes the LPD and FPD.

System software can request that domains and blocks be reset or powered down by writing to the PMC and PSM global registers. See Reset Service Requests.

The cause of device-level resets is recorded in the CRP RESET_REASON register.