Q&A Programming Sequence

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The Q&A programming sequence includes:

  1. If required, set WDP bit (to enable protection against accidental clearing).
  2. Configure the first and second window count registers according to the application requirements.
  3. Set the interrupt position in the second window using the Funct_Ctrl [SBC] and [BSS] bits.
  4. If required, enable the second sequence timer function using the [SSTE] bit. The fail counter is always enabled and the [PSME] bit has no meaning in Q&A mode.
  5. Programmed the seed value into the Token_FB [SEED] bit field.
  6. Program the first feedback[ configuration into the Token_FB [FDBK] bit field.
  7. Program the watchdog mode using the Funct_Ctrl [WM] bit.
  8. Enable the watchdog timer using the Enable_and_Status [WEN] bit.
  9. Enable register write protection by setting the WProt [MWC] bit = 1 and write the Token_Resp [ANS] register field to start the first question-answer sequence:

    After window mode is enabled, a write response to the Token_Resp [ANS] register field triggers the start of the first window. Each Subsequent token-response sequences start after a correct answer to the previous sequence run.

    The default value of the Enable_and_Status [ACNT] field is “00” and after step 9, this field updates to “11.”

    Step 9 also takes into account the first feedback configuration for the first time. Subsequently, feedback configuration updates are considered at each new sequence run.

    The first token-response is presented to the Enable_and_Status register after step 9. Subsequent tokens are presented at each new sequence run.

  10. Write three correct responses to the Token_Resp register within the first window interval. The first window always completes. The second window starts if the watchdog has received three correct responses in the first window.
  11. Wait for the watchdog system interrupt in the second window. Token early, Enable_and_Status [TERL] bit.
  12. Change the token feedback configuration if required.
  13. Write the last response during the second window. This ends the seconds window interval early.
    Note: The second window might time out in the absence of any response, expire waiting for the fourth (last) correct response, or finish earlier than the programmed value after receiving the fourth (last) correct response.

    If it times out or expires, the watchdog restarts with the first window and expects the same question-answer sequence (i.e., the question cannot be changed by token feedback configuration).

    The Enable_and_Status [ACNT] bit does not change with an incorrect response. Each incorrect response is considered a bad event and increments the fail counter. With a correct byte response, the [ACNT] status updates to “11.”

    There can be more than one response possible in the second window due to incorrect responses.

  14. The next question is presented in the Enable_and_Status register.
  15. Repeat steps 10-13.
  16. After enabled in Q and A mode, the window mode can be disabled only when the fail counter is zero. An attempt to disable the watchdog does not change the fail counter in Q and A mode.
Note: After generating the SWDT_RESET, the watchdog stops running and the [WEN] bit auto-clears.

The response conditions are summarized in the following table. In most cases, the fail counter [FCV] either increments (+1) for a good event or decrements (-1) for a bad event. If the fail counter is 7 and an bad event occurs, then a system reset is put into motion. If [ACNT] does not advance, then it stays at the same count.