QSPI Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are two register overview tables for the QSPI.

  • QSPI register overview
  • PMC_IOP_SLCR and CRP related registers for QSPI system control, clocking, and reset.

The QSPI registers are listed in the following table. The base address for these registers is 0xF103_0000.

Table 1. QSPI Register Set
Function Register Name Address Offset Access Type Description
I/O signals Rx_Clk_Dly 0x03C R/W RX clock delay bypass enable
DMA


            DMA_Dst_Addr_L
        


            DMA_Dst_Addr_U
        

0x800

0x828

W DMA destination memory address, low

DMA destination memory address, high

DMA DMA_Dst_Size 0x804 W DMA transfer size with start feature
DMA DMA_Dst_Status 0x808 R/WTC DMA status
DMA DMA_Dst_Ctrl 0x80C R/W DMA control reg 1
Commands DMA_Dst_Ctrl2 0x824 R/W DMA control reg 2
DMA interrupts


            DMA_Dst_ISR
        


            DMA_Dst_IMR
        


            DMA_Dst_IER
        


            DMA_Dst_IDR
        

0x814
0x820
0x818
0x81C

R
W
W
R

DMA interrupt status
DMA interrupt mask
DMA interrupt enable
DMA interrupt disable

Configuration GQSPI_Cfg 0x100 Mixed Configuration
Configuration GQSPI_En 0x114 RW Controller enable
Data flow Tx_Data 0x11C W Transmit data word
Data flow Rx_Data 0x120 R Receive data word
Write protect GPIO_WProt 0x130 RW GPIO write protect
I/O signals LPBK_Dly_Adj 0x138 RW Loopback clock delay adjustment
Commands Cmd_FIFO_Data 0x140 W Word port for FIFO command
Controller mode Mode 0x144 RW Controller mode set
FIFO control GQSPI_FIFO_Ctrl 0x14C W TX/RX FIFO control, generic I/O mode
PIO interrupts


            GQSPI_ISR
        


            GQSPI_IMR
        


            GQSPI_IER
        


            GQSPI_IDR
        

0x104

0x110

0x108

0x10C

R/WTC
W
W
R

Polling status and RX/TXFIFO interrupt states
Interrupt mask
Interrupt enables
Interrupt disable

Data flow Tx_Thresh 0x128 RW TXFIFO threshold level
Data flow Rx_Thresh 0x12C RW RXFIFO threshold level
Controller commands GQSPI_GF_Thresh 0x150 RW FIFO threshold level
Polling GQSPI_Poll_Cfg 0x154 RW Poll configuration
Polling GQSPI_Poll_TO 0x158 RW Polling timeout