QSPI System-Level Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The system-level registers related to the QSPI controller are listed in the following table.

Table 1. QSPI System-level Registers
Register Name Description Access Type
Clocks and reset control registers in the CRP register module
QSPI_REF_CTRL QSPI reference clock frequency control RW
RST_QSPI QSPI reset control bit RW
DMA transaction control registers in PMC_IOP_SLCR
QSPI_Coherent Define transaction coherency and buffer-ability policy RW
QSPI_Route Route through FPD CCI (APU L2- cache coherent) or bypass it (non-coherent) RW
QSPI_QoS QoS traffic type; recommend setting to best effort, BE RW
PMC MIO Pin Routing control registers in PMC_IOP_SLCR

(pins 0 to 52)

Control the MIO pin routing RW