Quad SPI Signals

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

In QSPI24/QSPI32 boot modes, MIO[6:0] for single device/dual-stacked device setups, or MIO[12:0] for dual-parallel device setups are configured by the BootROM to use:

  • Default drive strength (8 mA)
  • Default slew rate (slow)
  • Default weak pull-ups (enabled)
  • Enables the Schmitt trigger input
  • Disables the 3-state override

The remaining MIOs are not set by the BootROM and remain at their default state. If a secure lockdown occurs during boot, the BootROM sets the PMC_GLOBAL TRISTATE_OVERRIDE register to force all I/Os into a tristate mode. This register is then reserved for use by the PLM firmware.

The following table lists the bidirectional PMC multiplexed I/Os (MIOs) and their functions used in the quad SPI boot mode setup.

Table 1. Quad SPI Boot Mode Signals
PMC MIO Pin Signal Name Description
0 QSPI0_CLK QSPI0 clock output
4 QSPI0_IO[0] I/O pin used as MOSI in 1-bit mode

I/O pin used as the lower QSPI0_IO[0] in 2-bit or 4-bit single or dual-stacked setups, and in 8-bit dual-parallel setups

1 QSPI0_IO[1] I/O pin used as MISO in 1-bit mode

I/O pin used as the lower QSPI0_IO[1] in 2-bit or 4-bit single or dual-stacked setups, and in 8-bit dual-parallel setups

2 QSPI0_IO[2] I/O pin used as the lower QSPI0_IO[2] in 4-bit single or dual-stacked setups, and in 8-bit dual-parallel setups
3 QSPI0_IO[3] I/O pin used as the lower QSPI0_IO[3] in 4-bit single or dual-stacked setups, and in 8-bit dual-parallel setups
5 QSPI0_CS_b Active-Low chip select output that enables QSPI0 (lower) flash device
12 QSPI1_CLK QSPI1 clock output
8 QSPI1_IO[0] I/O pin used as MOSI in 1-bit mode

I/O pin used as the upper QSPI1_IO[0] in 2-bit or 4-bit dual-stacked setups, and in 8-bit dual-parallel setups

9 QSPI1_IO[1] I/O pin used as MISO in 1-bit mode

I/O pin used as the upper QSPI1_IO[1] in 2-bit or 4-bit dual-stacked setups, and in 8-bit dual-parallel setup

10 QSPI1_IO[2] I/O pin used as the upper QSPI1_IO[2] in 4-bit dual-stacked setups, and in 8-bit dual-parallel setups
11 QSPI1_IO[3] I/O pin used as the upper QSPI1_IO[3] in 4-bit dual-stacked setups, and in 8-bit dual-parallel setups
7 QSPI1_CS_b Active-Low chip select output enables QSPI1 (upper) flash device
6 QSPI_LPBK_CLK I/O pin used for loopback clock

The loopback clock is an internal clock signal that is routed through the output buffer to this pin and returned back through the pin's input buffer to the quad SPI controller for I/O delay compensation.

When the quad SPI device clock frequency is >37.5 MHz, the loopback clock must be enabled in the CIPS IP core and the MIO[6] must be left unconnected on the board.

When the quad SPI device clock frequency ≤37.5 MHz, the loopback clock should be disabled in the CIPS IP core so MIO[6] is not used by the quad SPI controller. If the interface is not run at >37.5 MHz, the MIO[6] can be used as another peripheral I/O.