The RPU memory protection unit (MPU) works with the CPU's L1 memories to control the accesses to and from the TCMs, caches, and external memory.
For a detailed description of the MPU, see the Cortex-R5F Technical Reference Manual.
The MPU partitions memory into regions and sets individual protection attributes for each region. When the MPU is disabled, no access permission checks are performed and memory attributes are assigned according to the default memory map. The MPU divides memory into a maximum of 16 regions.
The following can be specified for each region using the MPU memory region programming registers:
- Region base address
- Region size
- Sub-region enables
- Region attributes
- Region access permissions
- Region enable