Received frames with optional FCS are written to receive buffers in system memory. The memory start location for each receive buffer is stored in the receive buffer descriptor table at an address location pointed to by the value in the receive-buffer queue pointer registers.
Each receive buffer start location is a word address. The start of the first memory buffer in a frame can be offset by up to three bytes depending on the value written to bits [14] and [15] of the network configuration register. If the start location of the AXI buffer is offset the available length of the first AXI buffer is reduced by the corresponding number of bytes.
There are six descriptor words per entry to provide a 44 or 48-bit address for the DMA AXI interface, see Descriptor Length.
Bit | Description |
---|---|
31:3 | Starting RX memory buffer address, bits [31:3]. Bits [47:32] are held in descriptor entry word 3. |
2 |
Timestamp enable: |
1 |
Wrap enable: |
0 |
Data ownership: |
Field | Description |
---|---|
31 | Global all ones broadcast address detected. |
30 | Multicast hash match. |
29 | Unicast hash match. |
28 | I/O address match. |
27 | Specific type address register match found, bit [25] and [26] indicate the specific address register that caused the match. |
26:25 |
Address register match indicator: If more than one specific address is matched, only one is indicated with priority 4 down to 1. |
24 |
Indicates different information when the RX checksum offloading is enabled or disabled. |
23:22 |
Indicates different information when the RX checksum offloading is enabled or disabled. If more than one specific type ID is matched, only one is indicated with priority 4 down to 1. |
21 |
VLAN tag detected: type ID of |
20 |
Priority tag detected: type ID of |
19:17 | VLAN priority: only valid if bit [21] is set. |
16 | Canonical format indicator (CFI) bit: only valid if bit [21] is set. |
15 |
End of frame: when set, the buffer contains the end of a frame. If end of frame is not set, then the only valid status bit is start of frame bit [14]. |
14 |
Start of frame: when set, the buffer contains the start of a frame. If both bits [15] and [14] are set, the buffer contains a whole frame. |
13 |
Indicates different information when the ignore FCS mode is enabled or disabled. • This bit is zero if ignore FCS mode is disabled. • When ignore FCS mode is enabled, bit [26] is set in the network configuration register. The per-frame FCS status indicates the following: 0: Frame had good FCS 1: Frame had bad FCS and if the ignore FCS mode is enabled, the frame is copied to memory |
12:0 | These bits represent the length of the received frame that could
include FCS if the FCS discard mode is enabled or disabled. • FCS discard mode disabled: Bit [17] is cleared in the network configuration register. The least significant 12 bits for length of frame include FCS. • FCS discard mode enabled: Bit [17] is set in the network configuration register. The least significant 12 bits for length of frame exclude FCS. |
Word | Field | Description |
---|---|---|
Word 0 | 31:0 | Timestamp enable, wrap enable, ownership. |
Word 1 | 31:0 | Miscellaneous fields. |
Word 2 | 15:0 | Upper sixteen AXI address bits [47:32]. |
31:16 | Not used. | |
Word 3 | 31:0 | Not used. |
Word 4 | 29:0 | Timestamp, nanoseconds. |
31:30 | Timestamp, seconds, bits [1:0]. | |
Word 5 | 3:0 | Timestamp, seconds, bits [5:2]. |
31:4 | Not used. |