Bit  of the network configuration register is the pause enable control for reception. If this bit is set and a non-zero pause quantum frame is received, transmission pauses.
If a valid pause frame is received, then the pause time register is updated with the new frame's pause time regardless of whether a previous pause frame is active. An interrupt (either bit  or bit  of the interrupt status register) is triggered when a pause frame is received, but only if the interrupt is enabled (bit  and bit  of the interrupt mask register). Pause frames received with non-zero quantum are indicated through the interrupt bit  of the interrupt status register. Pause frames received with zero quantum are indicated on bit  of the interrupt status register.
When the pause time register is loaded and the frame currently being
transmitted is sent, no new frames are transmitted until the pause time reaches zero.
The loading of a new pause time, and the pausing of transmission, only occurs when the
controller is configured for full-duplex operation. If the controller is configured for
half-duplex there is no frame is defined as having a destination address that matches
either the address stored in specific address register 1 or if it matches the reserved
0x0180C2000001. It must also have the MAC control frame type
0x8808 and have the pause opcode of
Pause frames that have FCS or other errors are treated as invalid and are discarded. IEEE Std 802.3 pause frames that are received after priority-based flow control (PFC) is negotiated are also discarded. Valid pause frames received increment the pause frames received statistic register. The pause time register decrements every 512-bit times once transmission has stopped. For test purposes, the retry test bit can be set (bit  in the network configuration register) which causes the pause time register to decrement every tx_clk cycle when transmission has stopped.
The interrupt (bit  in the interrupt status register) is asserted whenever the pause time register decrements to zero (assuming it was enabled by bit  in the interrupt mask register). This interrupt is also set when a zero quantum pause frame is received.