Rate Control

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

Each DMA channel can be independently programmed to issue transactions on a periodic basis. Higher priority channels can have a shorter interval between transactions. The lower priority channels can have a longer interval between transactions. The issue rate is independently controlled for each channel using an interval count that is programmed into the CH_RATE_CTRL [CNT] bit field. Rate control is enabled by setting CH_CTRL0 [RATE_CTRL] bit field = 1. There are 16 pairs of registers for rate control (8 channels).

Enabling rate control causes the DMA channel to copy the interval count, CH_RATE_CTRL [CNT] bit field, into the channel's decrementing counter. This counter is decremented with every clock cycle. When the counter reaches 0, the DMA channel issues a transaction to the arbiter and again copies the interval count into the decrementing counter. The channel waits for the counter to reach 0 again, and then issues another transaction and reloads the counter. The cycle continues until disabled by setting [RATE_CTRL] = 0.

Tip: When rate control is enabled, the read data transaction frequency is always equal to or less than the programmed rate control frequency (1/rate control count).