Real-time Processing Unit

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The Versal adaptive SoC real-time processing unit (RPU) provides predicable software execution times using Arm® Cortex®-R5F processors for real-time applications. The RPU is located in the LPD of the PS. Each processor includes separate L1 instruction and data caches and tightly coupled memories (TCM) that are dedicated to their RPU CPU cores to narrow down the deterministic behavior for real-time data processing applications. The CPUs feature out-of-order execution that is coupled with a single/double precision floating point unit (FPU). The processor also includes a general interrupt controller (GIC PL-390) to receive system interrupts. System memory is cacheable, but the TCM memory space is non-cacheable.

The RPU is a dual MPCore that can be configured for dual-processor or lock-step mode. The dual-processor mode provides higher performance. The lock-step configuration provides a high level of reliability for functional safety.

The RPU can execute instructions and access data from its TCMs, the OCM memory, the main DDR memory, and other system memories. When addressing system memory, the transactions can be routed directly to the NoC for accessing DDR memory, or through the APU cache coherent interconnect (CCI) in the FPD for hardware coherent transactions with the APU’s L2 cache memory.

The TRM describes the architecture and the programming model for the controllers and other functional units. Linux and bare-metal software stacks execute in the APU and RPU in a homogeneous or a heterogeneous environment. Software environments within the RPU can be partitioned on a hardware basis. The software programming environment is described in the Versal Adaptive SoC System Software Developers Guide (UG1304).

Each Cortex-R5F core includes:

  • 32 KB L1 instruction cache with ECC
  • 32 KB L1 data cache with ECC
  • FPU: single and double precision
  • Embedded trace microcell (ETM) to support real-time debug and trace; ETM communicates with the Arm CoreSight™ debug system

Each RPU processor can be individually configured for inter-processor interrupts (IPI). The RPU processors have a common power island. The TCMs are divided into four banks with four power island controls. However, all power islands must be enabled to access any of the TCMs.


This chapter describes general processor features and the implementation included in the AMD Versal™ device. A list of Arm documentation is listed in Arm Documents section in the appendix.