There are many clock frequency dividers in the PMC, LPD, FPD, and CPM that provide a reference clock for each block or group of blocks. See the Clock Distribution Diagram for an overview.
The PMC, PS, and CPM clock dividers all have similar programming models. The clock control registers select the PLL source clock, define the 10-bit divider value, and enable the divider clock output. The clock divider register sets include: