Reference Clock Frequency Dividers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are many clock frequency dividers in the PMC, LPD, FPD, and CPM that provide a reference clock for each block or group of blocks. See the Clock Distribution Diagram for an overview.

The PMC, PS, and CPM clock dividers all have similar programming models. The clock control registers select the PLL source clock, define the 10-bit divider value, and enable the divider clock output. The clock divider register sets include:

  • CRP register module for PMC clocks
  • CRL register module for LPD clocks
  • CRF register module for FPD clocks
  • CPM4_CRX register module for CPM4 clocks