Register-driven DMA Mode

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

In SDMA mode, the controller provides a simple programming model that is controlled by registers in the SD_EMMC register module. The controller interacts with these registers to control the SDMA engine to transfer data from the flash memory to system memory.

The DMA controller interfaces to the PMC IOP switch with an AXI interface. The DMA controller reads and writes data to the block buffer. The RX and TX interfaces access the block buffer to transmit and receive data blocks on the SD I/O interface.

SDMA mode provides a programmed I/O (PIO) interface to software. The SDMA maintains the block transfer counts for the PIO operations.

The DMA memory transactions can be routed through the FPD CCI for cache coherency with the APU L2 cache or a non-coherent path including a NoC port to access system memory or AXI routing to the OCM memory. Software selects the AXI transaction route using a PMC_IOP_SLCR register to program the DMA transaction route for the DMA transfer.