Routing and Coherency Controls

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The programmable transaction routing and coherency controls are summarized in the following table.

Table 1. Transaction Routing and Coherency Controls
Transaction Host Routing Control AxCACHE Signal Control
LPD
RPU0 processor LPD_INT_CSR RPU0_Route [routing] Generated by the R5F processor
RPU1 processor LPD_INT_CSR RPU1_Route [routing] Generated by the R5F processor
LPD DMA ch 0:7 LPD_INT_CSR DMA_Route [routing] Individual channel registers: PS_DMA CH_DATA_ATTR
PSM processor PSM_INT_CSR PSM_Route [routing]  
GEM 0 LPD_IOP_SLCR GEM0_Route [routing] LPD_IOP_SLCR GEM0_Coherent [GEM0_AXI_COH]
GEM 1 LPD_IOP_SLCR GEM1_Route [routing] LPD_IOP_SLCR GEM1_Coherent [GEM1_AXI_COH]
USB 2.0 LPD_IOP_SLCR USB_Route [routing]  
PL
PL_AXI_LPD LPD_INT_CSR PL_AXI_LPD_Route [routing] Defined by PL fabric
PMC
PPU processor PMC_INT_CSR PPU_Route [routing]  
PMC DMA 0 PMC_INT_CSR DMA0_Route [routing]  
PMC DMA 1 PMC_INT_CSR DMA1_Route [routing]  
JTAG DAP controller PMC_INT_CSR DAP_Route [routing]  
PMC SYSMON PMC_INT_CSR SysMon_Route  
PMC IOP
SD_eMMC 0 DMA PMC_IOP_SLCR SD0_Route [routing] PMC_IOP_SLCR SD0_Coherent [SD0_AXI_COH]
SD_eMMC 1 DMA PMC_IOP_SLCR SD1_Route [routing] PMC_IOP_SLCR SD1_Coherent [SD1_AXI_COH]
QSPI DMA PMC_IOP_SLCR QSPI_Route [routing] PMC_IOP_SLCR QSPI_Coherent [QSPI_AXI_COH]
OSPI DMA PMC_IOP_SLCR OSPI_Route [routing] PMC_IOP_SLCR OSPI_Coherent [OSPI_AXI_COH]