SD Clocks

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

System Clocks

The controller receives the following system clocks from the PMC clock controller:

  • SDx_REF_CLK reference clock for the DIV_CLK module and controller
  • SD_DLL_REF_CLK reference clock for SD DLL module
  • PMC_IRO_CLK for the AXI DMA and programming interfaces
Note: Two clock frequency restrictions between the SDD DLL and the reference clocks are included in the Flash Memory Controller Clock Frequency Requirements section of the Clocks chapter.

Interconnect Interface Clocks

There are two AXI interfaces and they are both clocked by PMC_IRO_CLK.

  • AXI 32-bit slave interface for data and control register programming
  • AXI 32-bit master interface for DMA

Controller Clock

The controller logic is always clocked by the DIV_CLK output from 10-bit divider clocked by the SDx_REF_CLK reference clock signal.

I/O Interface Clock

The controller supports a wide range of I/O clock frequencies including 400 kHz discovery and 25, 50, 100, and 200 MHz frequencies (some with double data rate).

The overall clock architecture is shown in the Clock Block Diagram. The controller always drives the I/O interface clock, SDx_CLK from one of two possible sources: DIV_CLK from the clock divider and three clocks from the DLL module. The clock source depends on the desired I/O clock frequency:

The I/O interface clocking is described in the I/O Clock Functionality section.