SD Flash Interface Signals

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The following table lists the SD flash interface signals.

For boot pin planning, see the MIO Boot Interfaces section. The SD MIO signals are also listed in the first PMC MIO signal table in MIO-at-a-Glance Tables

Note: In the case of a default speed (DS) mode, the outputs are driven on the negative edge of the SD_CLK.
Table 1. SD Flash Interface Signals
Signal Name Description MIO EMIO
SD v2.0 SD v3.0 MIO-at-a-Glance Table I/O Signal Port Name I/O
Route Signals as a Group

SD_CLK

Clock output CLK O    
SD_CMD Command CMD I/O    
SD_DATA [0:3] Four data, address, control I/O signals D [0:3] I/O    
- SD_SEL Select signal is automatically asserted when SD3.0 mode is selected. Select signal enables an external voltage translator to switch from 3.3V to 1.8V to operate the SD card at the highest performance supported. SEL O    
- SD_DIR_CMD DIR_CMD output, determines if the command is an input or output. DIRC O    
- SD_DIR0 DIR 0 output determines if Data 0 is an input or output. DIR 0 O    
- SD_DIR1_2_3 DIR 1 output determines if Data [1:3] direction is an input or output. DIR 1 O    
Free Routing Optional Signals 1    

SD_DETECT2

Card detect input indicator CD I    

SD_WP

Write protect input indicator WP I    

SD_BUSPWR

Bus power control output PWR O    
  1. The free option signals are essentially DC and do not necessarily need to be in the same pinout group as the I/O, clock, and command signals.
  2. The SD_DETECT signal is separate from the traditional SD_DATA[3] signal.