SD Register Boot Settings

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The BootROM sets configuration registers that apply to each boot mode. For SD boot modes, the BootROM sets the registers to the initial values shown in the following tables.

Table 1. SD0 Register Boot Settings
Register Name Base Address Register Value Description
SD0_REF_CTRL 0xF126_0124 0x0100_1200 Select PPLL divided by 18 (DIVISOR), clock enabled
SD0_Clk_Ctrl 0xF106_0400 0x0000_0001 SD0 I/O feedback clock control MIO[38]
MIO_Bank1_Schmitt_En 0xF106_030C 0x00FF_D000 Enable Schmitt on SD0 MIO pins
MIO_Bank1_Tristate 0xF106_0204 0x0300_2FFF Disable 3-state override on SD0 MIO pins
RST_SDIO0 0xF126_0308 0x0000_0000 SDIO RST not asserted
SD0_Cfg_Reg1 0xF106_0410 0x0000_1E50 Base clock frequency, sync wake-up mode
SD0_CD_Ctrl 0xF106_044C 0x0000_0000 CD signal from SD/eMMC is used
SD0_Ctrl 0xF106_0404 0x0000_0000 SD mode enabled
SD0_Cfg_Reg2 0xF106_0414 0x0000_0FFC SD0 configuration setup
PMCPLL_CTRL 0xF126_0040 0x0002_4800 PMC PLL (PPLL) setup uses reset defaults ( REF_CLK multiplied by 72 (FBDIV) and divided by 4 (CLKOUTDIV))
Table 2. SD1 Register Boot Settings
Register Name Base Address Register Value Description
SD1_REF_CTRL 0xF126_0128 0x0100_1200 Select PPLL divided by 18 (DIVISOR), clock enabled
SD1_Clk_Ctrl 0xF106_0480 0x0000_0001 SD1 I/O feedback clock control on MIO[26]
MIO_Bank1_Schmitt_En 0xF106_030C 0x0200_07FB Enable Schmitt on SD1 MIO pins
MIO_Bank1_Tristate 0xF106_0204 0x01FF_F804 Disable 3-state override on SD1 MIO pins
RST_SDIO1 0xF126_030C 0x0000_0000 SDIO RST not asserted
SD1_Cfg_Reg1 0xF106_0490 0x0000_1E50 Base clock frequency, sync wake-up mode
SD1_CD_Ctrl 0xF106_04CC 0x0000_0000 CD signal from SD/eMMC is used
SD1_Ctrl 0xF106_0484 0x0000_0000 SD mode enabled
SD1_Cfg_Reg2 0xF106_0494 0x0000_0FFC SD1 configuration setup
PMCPLL_CTRL 0xF126_0040 0x0002_4800 PMC PLL (PPLL) setup uses reset defaults ( REF_CLK multiplied by 72 (FBDIV) and divided by 4 (CLKOUTDIV))