SD_eMMC I/O Signals

Versal ACAP Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2022-12-16
Revision: 1.5 English

The I/O signals are summarized in the following table and shown in PMC MIO Pins. The I/O group options must be assigned together. The free options can be assigned to either pin option.

Table 1. SD_eMMC Controller I/O Signals
MIO									EMIO
Signal Name			I/O	PMC MIO Pin				MIO-at-a-Glance Table	Signal Name	I/O
Signal Name				SD 0		SD 1
SD 2.0	SD 3.0	eMMC		A	B	C	D
A, B, C, D Group Options:
SD0_CLK SD1_CLK		eMMC0_CLK eMMC1_CLK	O	18	38	0	26	2
SD0_CMD SD1_CMD		eMMC0_CMD eMMC1_CMD	I/O	23	40	3	29	3
SD0_DATA[0] SD1_DATA[0]		eMMC0_DATA[0] eMMC1_DATA[0]	I/O	13	41	4	30	4
SD0_DATA[1] SD1_DATA[1]		eMMC0_DATA[1] eMMC1_DATA[1]	I/O	14	42	5	31	5
SD0_DATA[2] SD1_DATA[2]		eMMC0_DATA[2] eMMC1_DATA[2]	I/O	15	43	6	32	6
SD0_DATA[3] SD1_DATA[3]		eMMC0_DATA[3] eMMC1_DATA[3]	I/O	16	44	7	33	7
~	SD0_SEL SD1_SEL	eMMC0_DATA[4] eMMC1_DATA[4]	I/O	19	45	8	34	8
~	SD0_DIR_CMD SD1_DIR_CMD	eMMC0_DATA[5] eMMC1_DATA[5]	I/O	20	46	9	35	9
~	SD0_DIR0¹ SD1_DIR0	eMMC0_DATA[6] eMMC1_DATA[6]	I/O	21	47	10	36	10
~	SD0_DIR1¹SD1_DIR1	eMMC0_DATA[7] eMMC1_DATA[7]	I/O	22	48	11	27	11
Free Option Signals ²
SD0_DETECT³ SD1_DETECT		~	I	24	39	2	28	1
SD0_WP SD1_WP		~	I	25	37	1	50	0
SD0_BUSPWR SD1_BUSPWR		eMMC0_RST eMMC1_RST	O	17	49	12	51	12
The DIR0 signal controls the direction of the DATA[0] signal and DIR1 signal controls the direction of the DATA[1:3] signals for the external voltage level shifters. The free option signals are essentially DC and do not necessarily need to be in the same group as the I/O signals. The SDx_DETECT signal is separate from the traditional SDx_DATA[3] signal.