SLCR I/O Interface Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The system-level registers are summarized in the following table. These registers are used to route the two I/O signals to MIO device pins.

Table 1. I2C SLCR Registers
Register Name Address Access Type Description
MIO_PIN_0 + 0xF106_0000 + RW

52 Registers:
PMC MIO pin 0 to
PMC MIO pin 51

MIO_PIN_0 + 0xFF08_0000 + RW

26 Registers:
LPD MIO pin 0 to
LPD MIO pin 25