SLCR Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The UART system-level control registers (SLCR) are listed in the following table. The base address for the SLCR registers:

  • LPD_IOP_SLCR register module is 0xFF08_0000.
  • PMC_IOP_SLCR register module is 0xF106_0000 (for PMC MIO).
Table 1. UART System-Level Clock and Reset Registers
Register Name Bit Field Offset Address Access Type Description
LPD_IOP_SLCR APB Programming Interface Access Error Interrupt


            PARITY_ISR
        


            PARITY_IMR
        


            PARITY_IER
        


            PARITY_IDR
        

[perr_uart0_apb]
[perr_uart1_apb]

0x0714+

W1C, R
R
W
W

Parity error detected on APB programming interface write data
LPD_IOP_SLCR MIO Select


            LPD_MIO_Sel
        

[UART0_SEL]
[UART1_SEL]

0x0410

RW Select between PMC and LPD MIO muxes
LPD_IOP_SLCR MIO Pin Routing


            MIO_PIN_0
        

etc.

            MIO_PIN_25
        

[L0_SEL}
[L1_SEL]
[L2_SEL]
[L3_SEL]

0x000+ RW LPD mux MIO routing
PMC_IOP_SLCR MIO Pin Routing


            MIO_PIN_0
        

etc.

            MIO_PIN_51
        

[L0_SEL}
[L1_SEL]
[L2_SEL]
[L3_Sel]

0x000+ RW PMC mux MIO routing