SMID Register

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are twenty SMID registers in the XPPU register module. When an AXI transaction is received, the AXI_SMID is compared against all of the [SMID] bit fields in the SMID_xx registers. The [SMID_M] mask bit field can be used to ignore individual SMID bits, if desired.

When an AXI transaction SMID value matches a value in an SMID_xx [SMID] register bit field, the transaction can propagate successfully.

  • AXI_SMID & [SMID_M] == [SMID] & [SMID_M]

The SMID register bit fields are shown in the following table.

Table 1. XPPU SMID Register
Bit Field Bit Field Description
SMID [9:0] SMID to match with AXI_SMID value
SMID_M [25:16] SMID mask for AXI_SMID and [SMID] compare
SMID_R [30] If set, only read transactions are allowed
SMID_P [31] Write even parity for all three fields; bits [30, 25:16, 9:0]

For a matched entry, if it is enabled by the corresponding bit of the [permission] field (as defined by the PERM field shown in Table 1) and if the read only SMID_nn [SMID_R] bit is set, only read transactions are allowed and write transactions are not allowed.

Parity on RAM-based SMID Registers

The SMID registers are based in RAM memory. If the parity option is enabled, the parity bits must be computed and written by the software for each SMID register.

To provide integrity, the [SMID], [SMID_M], and [SMID_R] bit fields are even parity protected and continuously read by the hardware. If the SMID parity is enabled ( CTRL [MID_PARITY_EN] = 1) and a parity is detected in the RAM, the SMID parity interrupt is asserted and the SMID register is disabled.