There are three clocks associated with a SPI controller.
- SPIx_REF_CLK controller reference clock
- LPD_LSBUS_CLK for the APB programming interface
- SPIx_SCLK on SPI bus
Clock frequency guidelines are included in the I/O Peripheral Clock Frequency Requirements section.
Each controller is provided a SPIx_REF_CLK from the LPD clock controller. This clock is used by the majority of the controller logic. Reference clocks are programmed by the LPD clock controller using the CRL SPI0_REF_CTRL and SPI1_REF_CTRL registers.
I/O SCLK Clock
The I/O SCLK is generated by dividing down the SPI_REF_CLK using the Config [BAUD_RATE_DIV] bit field. The divide-down ratio options include /4, /8, /16, …, /256.
APB Programming Interface Clock
The controller is also clocked by the LPD_LSBUS_CLK for the APB programming interface. This clock is common to all LPD controllers on the IOP switch and is controlled by the LPD_LSBUS_CTRL register.