Scalar Engines

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The scalar engines include:

  • Real-time processing unit (RPU)
  • Application processing unit (APU)

Real-time Processing Unit

The RPU MPCore processor is integrated into the LPD subsystem of the PS as shown in the PS LPD Interconnect Diagram. The implementation and functionality of the Cortex-R5F processor is detailed in the Real-time Processing Unit chapter with additional information in the Arm documents.

The main features of the RPU:
  • Dual Arm® Cortex®-R5F cores
  • Lock-step and dual processor modes
  • Tightly coupled memories for predictive execution times

Application Processing Unit

The APU MPCore processor is integrated into the FPD subsystem. The implementation and functionality of the Cortex®-A72 processor is detailed in the Application Processing Unit chapter with additional information in the Arm documents.

The main features of the APU:
  • Dual Arm Cortex-A72 cores
  • VFPv4 floating point, NEON, Crypto extension
  • 48 KB instruction, 32 KB data caches
  • GIC-500 interrupt controller
  • 1 MB L2 Cache Coherent Interconnect (CCI)