Introduction
Introduction to Versal ACAP
Navigating Content by Design Process
Device Overview
Device-Level Block Diagram
System Features
Processing System
Processor Communications
Platform Management Controller
PMC Block Diagram
Features Supporting System Start-up
Applications
Software Code and Data Files
Embedded Processor Code
Data Packets
System Performance
Interconnect Features
Transaction Quality of Service
Device Comparisons and IP Versions
Comparisons to Previous Generation Devices
IP Block Versions
Devices with Encryption Disabled
Documentation
Versal ACAP Technical Reference Manual Outline
Additional Documents
Xilinx Documentation Navigator
Hardware Architecture
System Interconnect Diagrams
Device-Level Interconnect Diagram
PMC-PS-CPM Interconnect Diagram
PMC and PS Architectures
PS FPD Architecture
PS FPD Interconnect Diagram
PS FPD Functional Units
PS LPD Architecture
PS LPD Interconnect Diagram
PS LPD Functional Units
PS LPD I/O Signals
PMC Architecture
Platform Management Functionality
PMC Interconnect Diagram
PMC Functional Units
PMC I/O Signals
Integrated Hardware
DDR4 Memory Controller
PL Building Blocks
Network on Chip Interconnect
Embedded Memories
Test and Debug
Integrated Hardware Options
Summary of Hardware Options
AI Engine
Accelerator RAM
High-Bandwidth Memory Interface
Integrated Peripheral Options
100G Multirate Ethernet MAC
600G Channelized Multirate Ethernet
600G Interlaken with FEC
400G High-Speed Crypto Engine
Multistream Video Decoder Unit
PL Fabric Overview
PL Block Diagram
Adaptable Engines in PL
Digital Signal Processing Engine
Configurable Logic Block
Block RAM
UltraRAM
Device I/O Connectivity
Device-Level Diagram
MIO and Dedicated I/O Banks
I/O Buffer Pin Banks
GTY and GTYP Pipe Transceivers
PL HDIO Banks
DDR I/O Banks
Integrated Silicon
Monolithic Physical Layout Example
Si Interposer Design for High-bandwidth Memory Example
Platform Boot, Control, and Status
Overview
Versal ACAP Comparison to Previous Generation Devices
Non-Secure Boot Flow
Secure Boot Flow
Asymmetric Hardware Root of Trust Secure Boot
Configuration Update
Configuration Update with Key Revocation
PPK Revocation
SPK Revocation
Revocation as a Tamper Penalty
Symmetric Hardware Root of Trust Secure Boot
Configuration Update
Configuration Update with Partition Revocation
Boot Image
PDI Size Estimation
Boot Header
Boot Modes
JTAG Boot Mode
Octal SPI Boot Mode
Octal SPI Register Boot Settings
Octal SPI Signals
Single Device Interface
Dual-Stacked Interface
Quad SPI Boot Mode
I/O Configuration Detection
Quad SPI Register Boot Settings
Quad SPI Signals
Single Device Interface
Dual-Stacked Interface
Dual-Parallel Interface
SD Boot Modes
SD Register Boot Settings
SD Signals
SD2.0 Interface
SD3.0 Interface
eMMC1 Boot Mode
eMMC1 Register Boot Settings
eMMC1 Signals
eMMC1 Interface
SelectMAP Boot Mode
SelectMAP Pattern and Bit Order
SelectMAP Sequence
SelectMAP Register Boot Settings
SelectMAP Signals
SMAP I/O Signals
Single Device Interface
Multiple Device Interface
Ganged Device Interface
Platform Management
Functional Safety Management
Single Point Fault Detection
Common Cause Failure Detection
Latent Fault Detection
Isolation Features
Additional Features
Dynamic Function eXchange
Power Management
Power Modes
Security Management
Tamper Monitoring and Response
Secure Key Storage and Management
Key Selection
Battery-Backed RAM Key
eFUSE Key
Key Update Register
Boot Header Key
Storing Keys in Encrypted Form (Black)
Physically Unclonable Function
Key Management Summary
User Access to Xilinx Hardware Cryptographic Accelerators
PL Soft Error Mitigation
PMC and PS System Error Management
Platform Hardware Reference
Hardware Boot Events
Boot Header Register Initialization Feature
Device State After RCU BootROM
PL-PMC GPI and GPO Port Signals
Software Platform Service Requests
Power and Isolation Requests
Reset Service Requests
CoreSight Wake-Up Requests
Hardware Allocated to RCU BootROM Code
RCU Allocated Registers
Hardware Allocated to PLM Firmware
PLM Allocated Functionality
PLM Allocated Memory
PLM Allocated Registers
BootROM Error Code Table
Device Identification
Address Maps and Programming Interfaces
Address Maps
High-level Address Map
4 GB Address Map by Address
4 GB Address Map by Name
NoC Address Map
Programming Interfaces
Programming Interfaces Listed by Block/Subsystem
APB, AXI Programming Interfaces
NPI Programming Interface
CFU Programming Interface
NPI Register Modules
Signals, Interfaces, Pins, and Controls
Power and PMC Dedicated Pins
Power Pins
PMC Dedicated Pins
Multiplexed I/O Signals and Pins
MIO-at-a-Glance Tables
PMC MIO Pins
LPD MIO Pins
MIO Routing Considerations
MIO-EMIO Interface Routing Options
MIO Pin Buffer Controls
Input Buffer Control Registers
Output Buffer Control Registers
MIO Pin Routing
MIO Routing Diagram
MIO Routing Control Registers
MIO Routing Functionality Details
MIO Pin Programming Example
PCIe Resets on MIO Pins
Engines
Engines Overview
Scalar Engines
Intelligent Engines
AI Engine
DSP Engine
Adaptable Engines
DMA Units
Processor Support Units
Processor Communications
Application Processing Unit
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
FPD Block Diagram
APU MPCore Functional Units
System Interfaces
Memory Space
Execution Pipelines
CPU Pipeline
FPU Pipeline
NEON Pipeline
Cryptography Engine
APU Address Model
Virtualization
Server Architecture
Processor Counters
Applications
Physical Counter
Virtual Counters
Private Counters
Programming
PS FPD Interrupts
Hardware Interrupts
GIC-500 Interrupt Controller
Exception Levels
Virtual Interrupts
Interrupt Translation Services
LPI and ITS Cache Updates
Register Reference
Processor Control and Status Registers
GIC Registers
Real-time Processing Unit
Features
Comparison to Previous Generation Xilinx Devices
Cortex-R5F Processor Implementation
System Perspective
Block Diagram
AXI System Interfaces
Operating Modes
Lock-Step Architecture
Configuration Registers
Power Modes and States
Address Maps
CPU Local and Global Memory Map
Memory Map Diagram
Processor Memory Datapaths
Tightly-coupled Memories
Memory Error Detection and Correction
RPU Memory Protection Unit
Interrupts
System Interrupts Generated by RPU
GIC Interrupt Controller
Block Diagram
Software Generated Interrupts
Shared Peripheral Interrupts
SPI Interrupt Sensitivity
Interrupt Prioritization
System Errors Generated by RPU
Test and Debug
Interrupt Injection Mechanism
Events and Performance Monitor Unit
Register Reference
Processor Control and Status Registers
LPD DMA Controller
Features
Comparison to Previous Generation Devices
System Perspective
Block Diagram
Functional Units
Common Buffer
System Interfaces
AXI Read Arbiter
AXI Write Arbiter
Memory Coherency
PL Flow Control Interface
Programming Guide
Channel Block Diagram
Modes and States
Simple Mode Programming
Sequence Steps
Descriptor Mode Programming
Data Flow
Model
Buffer Descriptor Format
Decriptor Format
Linked List Mode Use Case
Linear Descriptor Use Case
Linked-List Descriptor Use Case
Hybrid Descriptor Use Case
Buffer Descriptor Summary
Interrupt Handling
Done Interrupt Accounting
Over Fetch
Transaction Control
Outstanding Transactions
Rate Control
PL Flow-Control Interface
Flow-Control Interface Considerations
Flow-Control Programming Model
Attached to the SRC
Channel Reading from a Flow Controlling a PL Destination
Channel Writing to a Flow Controlling the PL Slave
Interrupts
Descriptions
Transaction Security
Channel Pause
Coming Out of Pause
Programming Model for Changing DMA Channel States
Channel Enabled
Channel Disabled
Register Reference
DMA Channel Registers
I/O Flow Control Signals
Embedded Processor, Configuration, and Security Units
Overview
Platform Processing Unit
Features
Programming Model
Interrupts
System Interrupts
Authenticated JTAG
Tamper Event Monitoring and Response System
PMC Register Reference
PMC Global Registers
PMC Local Registers
Processing System Manager
Features
System Perspective
Interrupts
Reset
Processor State After Reset
PSM Register Reference
PSM Global Registers
PSM Service Requests
Power Islands
Wake-Up Service Requests
PSM Local Registers
PL Configuration
Configuration Frame Unit
Configuration Frame Interface
SBI for JTAG and SelectMAP
PMC Security Units
AES-GCM
SHA3-384
RSA/ECDSA
True Random Number Generator
Physically Unclonable Function
Secure Stream Switch
PMC DMAs
Interconnect
Overview
Features
Comparison to Previous Generation Xilinx Devices
MMUs
Interconnect Switches
AXI Timeout
AXI and APB Isolation
Xilinx Memory Protection Unit
Xilinx Peripheral Protection Unit
System Perspective
Network On Chip
PMC and PS Interconnect
Register Module Programming Interfaces
Transaction Hosts
System Management IDs
APU SMID Bits [3:0]
Interface Types
Transaction Attributes
Address
PMC and PS Perspectives
Data
System Management ID
Features
Comparison to Previous Generation of Devices
TrustZone Security
Features
Architecture
Security Profiles
PL Security
TrustZone Profile
AxCACHE
Quality of Service
Traffic Types
Sources
Safety Features
Poisoned Transaction
AXI Interconnect Switches
Switch Architecture
Conceptual Interconnect
Features
Switch Ingress Ports
iPort Protocol Integrity Checker
iPort Isolation
iPort Parity Unit
Switch Egress Ports
ePort Timeout
ePort Isolation
ePort Parity Unit
ePort Reset
Interconnect Switch Diagrams
PMC Interconnect
PMC IOP Interconnect
PSM Interconnect
LPD and OCM Interconnect
LPD IOP Interconnect
FPD Interconnect
FPD Auxiliary Interconnect
PS CPM Interconnect
Interconnect Channels and Ports
Interconnect Register Set Overview
Transaction Routes
Routing and Coherency Controls
CPM Transaction Route Use Cases
Block Diagram
PCIe Root Complex Mode
PCIe Endpoint Mode
CPM and CCI Transaction Route Restrictions
CCI AXI Port Routing Restriction
PCIe Root Port Mode Routing Restriction
PCIe Endpoint Mode Routing Restriction
OSPI Direct Access by PMC DMA via CCI
PL Interconnect Interfaces
PL to PS Interfaces
ACE Interface
ACP Interface
AXI Interface
PS to PL Interfaces
Register Reference
Shared Virtual Memory
System Perspective
APU Virtualization
Interrupt Virtualization
System Memory Management Unit
Features
Comparison to Previous Generation Xilinx Devices
SMMU TBU Instances
Address Translation Examples
Native, Non-Virtual
Virtual
Stream IDs
Memory Protection Functionality
Cache Coherent Interconnect
Features
Comparison to Previous Generation Xilinx Devices
Cache Coherency
Two-way Coherency
I/O Coherency
Snoop Filter
Snoop Filter Table Management
AXI Outgoing Ports
Striping NoC Interfaces
Transaction Attribute Management
QoS Response
CCI Register Reference
CCI CSR
CCI Core
Memory Space Protection
Types of Protection Units
Protection Units
Use Case Example
TrustZone Security
Xilinx Memory Protection Unit
Features
Versal ACAP Instances
System Perspective
Memory Regions
Access Checking Operations
SMID Validation
Security Validation
Block Diagram
Error Handling
AXI Transaction Signals
Configuration
XMPU Register Reference
XMPU Register Set
XMPU Write Lock
Xilinx Peripheral Protection Unit
Features
Instances
System Perspective
Protected Addresses
Transaction Checking Operations
SMID Checking
SMID Register
Aperture Permission Checking
Permission and TrustZone Registers
Aperture Register Map
Errors
XPPU Register Reference
XPPU Register Set
XPPU Write Lockdown
Interrupts and Errors
System Interrupts
System Interrupt Controllers
Sensitivity
IRQ System Interrupts
Register Reference
Interrupt Masking Registers
Inter-Processor Interrupts
Features
Comparison to Previous Generation Devices
List of SMID Profiles
System Perspective
List of Agents
Agent Communications
Interrupt Architecture
Interrupt Functionality
Interrupt Signal Mapping
Interrupt Signal Mapping
Message Passing Architecture
Messaging Diagram
Agent Example
Register Reference and Address Map
Control Registers
Register Write Lock Bit
Agent Interrupt Registers
Message Buffer
Programming Examples
Send an IPI Communication
Receive an IPI Communication
System Errors
Error Accumulator Modules
Types of Errors
Memory Errors
Interconnect Errors
Processor Errors
System Watchdog Timer Errors
System Software Errors
Functional Safety Errors
Security Errors
System Error Accumulator Registers
PMC Error Status Registers
PMC Error Status 1
PMC Error Status 2
PSM Error Status Registers
PSM Error Status 1
PSM Error Status 2
Error Status Register Mapping
Programming Model
Programming Interface
Timers, Counters, and RTC
Real-Time Clock
Features
Counter Module
Calibration
RTC Accuracy
External Clock Crystal and Circuitry
Interfaces and Signals
Registers
System Timestamp Counter
Triple-Timer Counters
Features
Block Diagram
Overflow Detection Functional Model
Interval Timing Functional Model
Event Timer Functional Model
Register Reference
TTC I/O Interface
TTC I/O Signals
System Watchdog Timers
Features
Window Timer Applications
Comparison to Previous Generation Devices
Watchdog Timer Instances
System Perspective
Block Diagram
Programming Interface
Watchdog Timer Clock Periods
Signals to the Timer
Signals Generated by the Timer
Window Watchdog Timer Mode
Windowed Waveform Diagram
Features and Options
Second Window Interrupt
Second Sequence Timer
Fail Counter
Windowed Basic Mode
Basic State Diagram
Basic Program Sequence Monitor
Basic Window Programming Sequence
Windowed Q&A Mode
Q&A State Diagram
Q&A Programming Sequence
Q&A Token Response Bits Table
Generic Watchdog Timer Mode
Generic Waveform Diagram
Generic Programming Sequence
Register Reference
Timer Register Set
System-Level Registers
SWDT I/O Interface
SWDT I/O Interface Signals
Memory
Overview
On-Chip Memory
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
States
Address Map
Memory Address Protection
ECC Protection
ECC Operations
Battery-Backed RAM
Accelerator RAM
External Memories
Embedded Addressable Memories
Small Storage Elements
PL Memory Building Blocks
Block RAM
UltraRAM
I/O Peripheral Controllers
CAN FD Controller
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
Object Layer
Logical Link Layer
MAC Transfer Layer
System Interface
System Signals
CAN FD Clocks
Controller Reset
System Interrupt
System Error
I/O Interface
Programming Model
Modes and States
Reset State
Mode Table
Mode Transition
Configuration Mode
Normal Mode
Sleep Mode
Snoop (Bus Monitoring) Mode
Loopback Modes
Self Loopback
Controller-to-controller Loopback
Protocol Exception Event State
Bus-Off Recovery State
Configuration Sequence
Message Transmission
Cancellation
Message Reception
Acceptance Filters
RX Buffer Usages
Disabled RX Buffer
Enabled RX Buffer
Register Reference
Control and Status
Message Space Data
System-level Control Registers
I/O Signal Reference
CANFD I/O Signals
Gigabit Ethernet MAC
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
Functional Units
System Signals
GEM Clocks
Controller Reset
System Interrupts
System Interfaces
DMA AXI Interface
APB Programming Interface
PL External FIFO Interface
I/O Interfaces
I/O Block Diagram
Clocks
Timestamp Unit Clock
Programming Model
Modes and States
10/100/1000 Operating Modes
Memory Packet Descriptors
Descriptor Length
DMA AXI Transactions
Burst Transactions
Transaction Routing and Coherency
Transmit Dataflow
Packet Buffer TX Functionality
TX Packets
TX Descriptor Entry Words
TX Descriptor Processing
MAC Transmitter
TX Broadcast Frames
TX Pause Frame
Quantum Time Base
Receive Dataflow
RX Packets
RX Packet Flow Monitoring
RX Descriptor Words
RX Descriptor Processing
MAC Receiver
Filtering
Hash Addressing
Capture All Frames
RX Broadcast Frames
VLAN Support
Wake-on-LAN Support
Magic Packet Events
Address Resolution Protocol
Specific Address 1 Filter Match
Multicast Hash Filter Match
Precision Timestamp Unit
MAC Pause Frames
RX Pause Frames
PFC Priority-based Pause Frame
Disable Copy of Pause Frames
Checksum Hardware
RX Checksum Offload
TX Checksum Offload
Register Reference
Control and Status
Statistics
System-Level Registers
AXI Transaction Control
I/O Signal Reference
MIO - RGMII Interface Signals
EMIO - GMII/MII Interface Signals
MDIO Interface Signals
Timestamp Unit Interface Signals
GPIO Controller
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
System Interface
System Signals
I/O Interface
Programming Model
Channel Block Diagram
Input Programming Model
Interrupt Programming Model
Output Programming Model
Registers
GPIO Register Descriptions
GPIO I/O Signals
MIO Signals
Assigned MIO Signals
EMIO Signals
I2C Controller
I2C Controller Features
Comparison to Previous Generation Devices
I2C System Perspective
Block Diagram
System Interface
System Signals
Clocks
Resets
System Interrupt
I/O Interface
I2C Register Reference
I2C Registers
I2C I/O Interface Routing Registers
I2C System-level Clock and Reset Registers
I2C Bus Interfaces
I2C Core Functionality
I2C Modes
Manager Modes
10-bit Addressing
Monitoring Mode
Response Mode
Glitch Filter
Test and Debug
LPD I2C Loopback Connection
I2C Programming Model
Reset Controller
Configure I/O Signals
Configure Clocks
Glitch Filter Note
Interrupts
Initiate Data Transfers
Master Read Using Polled Method
Manager Read Using Interrupt Method
Manager Write Using Interrupt Method
Monitor Mode
I2C Programming Sequences
I2C Software Routines
Reset
Get Options
Check Bus is Busy
Transmit FIFO Fill
Send Byte
Reset Hardware
Setup Master
Master Send
Master Receive
Master Send Polled
Master Receive Polled
Enable Slave Monitor
Disable Slave Monitor
Master Send Data
Master Interrupt Handler
Setup Slave
Slave Send
Slave Receive
Slave Send Polled
Slave Receive Polled
Receive Data
Slave Interrupt Handler
Set and Clear Options
Set SCLK Frequency
Get SCLK Frequency
Self-Test
SPI Controller
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
System Interface
System Signals
SPI Clocks
Controller Reset
I/O Interface Overview
Programming Model Overview
Modes and States
Master Mode
Slave Mode
Data Loopback Mode
Functional Diagram
FIFOs
Data Transfer
Register Reference
Controller Registers
System Level Registers
I/O Interface Signals
SPI I/O Signals
UART Controller
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
System Interface
System Signals
UART Clocks
Controller Reset
Modes and States
UART Functionality
Block Diagram
Baud Rate Generator
Transmit FIFO
Receive FIFO
Transmit Logic
Receive Logic
Interrupts
Operation
Data Transmission and Reception
Transmission
Reception
Error Bits
Overrun Bit
System and Diagnostic Loopback Testing
Baud Rate Divider
Character Frame
Hardware Flow Control
RTS Flow Control
CTS Flow Control
IrDA Functionality
Block Diagram
Transmit Encoder
Receive Decoder
Data Modulation
Interrupts
Flow Control Interrupts
Change State Interrupt
Timeout Interrupt
Error Interrupt
UART Registers
Controller Registers
SLCR Registers
Clock and Reset Registers
UART I/O Interface
UART I/O Signals
USB 2.0 Controller
Features
Comparison to Previous Generation Devices
System Perspective
High-Level Block Diagram
System Interfaces
System Signals
Clocks
Controller Resets
System Interrupts
System Error Signal
I/O Interface
Power
Programming Model
Host Mode Data Structures
Register Reference
Controller Registers
XHCI Registers
Host Capabilities, Offset, and Operations Registers
Port Status, Control, Host Interrupter, Event Ring, and Doorbell Registers
Miscellaneous Control, Status, and Capabilities Registers
Miscellaneous Configuration, Control, and User Registers
Device and Command Registers
System-Level Registers
LPD System-Level Registers
PMC System-Level Registers
Clock and Reset Registers
USB I/O Interfaces
USB ULPI I/O Signals
Port Indicator, Fault, and Power Select Signals
Flash Memory Controllers
Octal SPI Controller
Features
Boot Device
Nomenclature
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
Functional Units
System Interfaces
System Signals
OSPI Clocks
Controller Reset
System Interrupt
System Error
I/O Interface
Programming Model
Access Modes
Memory Access Modes
Polling Feature
Start-up Sequences
DMA Programming Model
DMA Features
Programming Steps
Source DMA
Source DMA Interrupts
Destination DMA
Destination DMA Interrupts
Configuration Restrictions
Interrupts
Controller Interrupts
Register Reference
OSPI Controller Registers
OSPI SRC DMA Registers
OSPI DST DMA Registers
System-Level Registers
OSPI I/O Interface
OSPI I/O Signal Table
Quad SPI Controller
Features
Comparison to Previous Generation Xilinx Devices
System Perspective
Block Diagram
Functionality
System Interfaces
System Signals
QSPI Clocks
QSPIx_CLK Loopback Feature
Controller Resets
System Interrupt
System Error
I/O Interface
Programming Model
Modes and States
Start-up
Reset
PIO Mode
DMA Mode
I/O Programming
Configurations
Clock Tap Control Settings
I/O Striping Function
Striping Programming Examples
Striping with Odd Byte Count
Command Words
Word Format
Immediate Data Field Usage
Programming
Programming Flowchart
DMA Data Transfer Length Examples
PIO Mode Programming Model
DMA Programming Model
Polling Programming Model
Register Reference
QSPI-specific Registers
QSPI I/O Interface
Wiring Diagrams
QSPI MIO Signal Table
SD v4.51 Controller
Features
Comparison to MPSoC Generation Devices
System Perspective
Block Diagram
Functional Units
System Interfaces
System Signals
SD Clocks
Controller Reset
System Interrupts
System Errors
I/O Interface
Modes and States
Speed Modes
States
Main Functionality
Command Controller
Transmit Control Unit
Receive Control Unit
Timeout Control
Data Transfer Block Buffer
I/O Functionality
Card Detect
Voltage Level Shifter Interface
Boot Sequence Example
I/O Clock Functionality
Clock Block Diagram
Controller Clock Start-up
I/O Clocking Modes
I/O Clock Frequency Control Sequence
25 MHz I/O Clock Range
Low-speed Clock Control Settings
Clock Frequency Divider Register Settings
High-speed I/O Clocking
DLL Programming Model
High-speed Clock Control Settings
High-speed TX Clocking
High-speed RX Clocking
Auto-tuning Unit in DLL
Manual DLL Programming Sequence
DLL Presets
DLL Programming Example
SD Commands
SD Command Response Registers
Register-driven DMA Mode
Descriptor-driven DMA Mode
Software Routines
Register Reference
System-Related Registers
Control and Status Registers
I/O Interface Control Registers
Command, DMA, and Data Registers
Interrupt and Status Registers
I/O Signals
SD_eMMC I/O Signals
Signaling Protocol
Clocks, Resets, and Power
Clocks
Clock Distribution Diagram
Cross-Domain Clock Routing Consideration
Clock Frequency Considerations
I/O Peripheral Clock Frequency Requirements
Flash Memory Controller Clock Frequency Requirements
Interconnect Clock Frequency Requirements
PMC Source Clocks
PLL Clock Generators
Features
Block Diagram
Reference Clock Frequency Dividers
Features
Block Diagram
Registers
PLL Clock Generator Registers
PMC Reference Clocks
LPD Reference Clocks
FPD Reference Clocks
Clock Monitor
Base Time Period
Calculate Threshold Counts
Monitored Clocks
Interrupts
Register Reference
Resets
Comparison to Previous Generation Xilinx Devices
System Perspective
Reset Source Figures
Reset Circuitry, EAM, and JTAG TAP Controller
PMC Reset Controller
Individual Reset Controllers
Programming Model
Reset Assertion Considerations
Reset Reason Register
Resets Overview
Device-Level Resets
Subsystem Resets
Debug Resets
POR_B Reset
Flowchart
System Integrity Monitoring
Power Supply Dropout
System Errors
System Monitoring Software
Reset Reference for Individual Blocks
PMC Block Resets
LPD Block Resets
FPD Block Resets
PL Resets
SoC Endpoint Resets
NPI Block Resets
NoC Resets
Persistent Registers
Global and Local
TrustZone Control
Power Control and Status
Clock and Reset Control
Miscellaneous Persistent Control Registers
Power
Power Diagram
Power Domains
Power Domain State Requirements
Power Islands
Test and Debug
Integrated Debug Overview
Integrated Debug Block Diagram
Debug Topics
JTAG TAP Controller
Features
System Perspective
TAP Controller Instruction Availability
JTAG TAP Instructions
JTAG Register Reference
ERROR_STATUS Register
EXTENDED_IDCODE Register
IDCODE Register
DNA Register
JTAG_STATUS Register
JTAG Controller Interface Pins
Arm DAP Controller
Arm DAP Registers
Arm DAP Instructions
CoreSight Architecture
Funnels
Debug Data Flow Diagram through Funnels
Cross-Trigger Interface Architecture
Versal ACAP CTI Units
CTI Summary Table
FPD CTI Ports
LPD CTI Ports
Trace Port Interface Unit
Data Flow Diagrams
Output Interface
TPIU I/O Signals
CoreSight Register Reference
Debug Timestamp Counter
Debug Packet Controller
DPC Interfaces
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Arm Documents
Please Read: Important Legal Notices
If the region is configured as secure, then only the secure request can access this
region.
If the region is configured as secure, then the read and write permissions are
independently checked to determine whether or not the transactions are allowed.
If the transaction is non-secure and the region is configured as secure, then
the check fails, and the transaction generates a system error.
If the region is configured as non-secure and the transaction is non-secure,
then read and write permissions are independently checked to determine whether or
not the transaction is allowed. If the check fails, the transaction is handled by
the error handler.