The SelectMAP boot mode is configured so that an external host (processor, controller, or another FPGA or SoC) can drive the interface to configure a single or multiple Versal adaptive SoC. The SelectMAP interface includes a 8-bit, 16-bit, or 32-bit data (SMAP_IO) bus, clock (SMAP_CLK), and control signals (SMAP_RDWR_b, SMAP_CS_b). The external host also needs to monitor the BUSY signal (SMAP_BUSY) for SelectMAP boot initiation and flow control.
When SelectMAP boot mode is detected during system start-up, the BootROM asserts the SMAP_BUSY signal and configures the SelectMAP interface. The SelectMAP interface setup includes configuring MIO signals, supervised boot interface (SBI), secure stream switch (SSS), and PMC DMA controller 1. After the SelectMAP interface is set up, the SMAP_BUSY signal is deasserted to indicate that the Versal device is ready to receive data from the SelectMAP host. The PMC controllers and blocks used to enable the path for the SelectMAP interface are highlighted in the Platform Management Controller Architecture chapter.
Because the SMAP_BUSY signal can be asserted at any phase during boot and configuration, this signal must be monitored to ensure the Versal device is ready to accept data on this interface. When the SMAP_BUSY signal is asserted during configuration, the SMAP_CS_b must be deasserted (within 24 SMAP_CLK clock cycles) to stop the data loading or the SBI FIFO (8 KB) buffer used for data processing overflows.