SelectMAP Sequence

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-12-16
Revision
1.5 English

The SelectMAP interface allows an external processor to load the boot and configuration data. The functional waveform in this section shows an example of the SelectMAP interface data, clock, and control signals operation to load data into the Versal ACAPs. To boot the Versal ACAP in SelectMAP, ensure that the dedicated boot mode pins are set to SelectMAP (MODE[3:0]=1010) and SMAP_RDWR_b is set to 0. Also, the dedicated REF_CLK pin (or REF_CLK[1:0] if in a stacked silicon interconnect (SSI) technology device) must be at a valid frequency and stable prior to the POR_B release.

The waveform shows the 16 byte bus detect pattern for the SelectMAP boot mode expected on the initial data cycles. For the majority of applications that only require SelectMAP data loading (writes), it is recommended to keep RDWR_B=0. The Versal ACAP samples the SelectMAP data pins on the rising SMAP_CLK edges. The waveform also shows an example BUSY response. The BUSY response time can vary but must be within 24 SMAP_CLK cycles. BUSY is clocked by the SMAP_CLK and does not transition back to low if the SMAP_CLK is stopped.

Figure 1. SelectMAP Data Loading