Sequence Steps

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English
The sequence steps for simple mode are outlined in this section.

Step 1

Wait until the DMA is in an idle state by reading the [STATE] field of CH_STATUS register and ensuring it is either 00 or 11. In the case where the DMA is in PAUSE state, follow the steps to bring the DMA out from PAUSE as described in Channel Pause.

Step 2

  • Ensure that the CH_CTRL0 [POINT_TYPE] bit is set = 0.
  • Program the data source buffer address LSB into register CH_SRC_DSCR_WD0 .
  • Program the data source buffer address MSB into register CH_SRC_DSCR_WD1 .

Step 3

  • Program the data destination buffer address LSB into register CH_DST_DSCR_WD0 .
  • Program the data destination buffer address MSB into register CH_DST_DSCR_WD1 .

Step 4

  • In simple DMA mode, both the SRC and DST transaction sizes must be programmed. The DMA uses the SRC transaction size but it also requires programming both registers. Program the source data size into the CH_SRC_DSCR_WD2 register.
  • Program the destination data transaction size into the CH_DST_DSCR_WD2 register. Make sure that the SRC and DST transaction sizes are the same.

Step 5

Optionally, enable an interrupt by setting INTR as a 1 in the PS_DMA.CH_DST_DSCR_WD3 and/or CH_SRC_DSCR_WD3 registers.

Step 6

  • If the source and destination buffer are allocated in non-cacheable memory or software flushes the caches, then:
    • Set the DMA_Route [routing] bit.
    • Program the [ARCACHE] and [AWCACHE] bits in the CH_DATA_ATTR register to indicate a cacheable transaction (e.g., 1111h).

Step 7

Enable the DMA channel to perform DMA transfers by setting the [EN] bit of CH_CTRL2 register. After enabling DMA, check for possible error conditions as described in Interrupts.