Signals Generated by the Timer

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The IRQ numbers for the watchdog timers are listed in the System Interrupts chapter. For I/O signals, refer to the end of this chapter.

Note: All of these signals are outputs from the watchdog timer. The system interrupts are level sensitive, active-High.
Table 1. Signals Generated by the SWDT Timer
Description Window Modes Generic Mode System Signal
Basic Q&A Name Destination

Main interrupt

Active-High interrupt output asserted when an interrupt bit in the Enable_and_Status register is set and not masked. Enable and status for the interrupts (e.g., G_CSR ).

Active-High:
SWDT_INT

IRQ
I/O

Applicable bits: [WINT], [WRP]. [GWEN], [GWS].
Reset to I/O signal to MIO/EMIO Asserted after a bad event (or when the fail counter overflows, if enabled). The controller auto disables itself (clears the [WEN] bit) and waits to receive a reset. Asserts on second expiration of the timeout counter.

Active-High:
SWDT_RST

I/O
Error signal assertion for PSM SWDT_ERROR

System error
I/O

Pending interrupt Asserted after a bad event. The controller auto disables itself (clears the [WEN] bit) and waits to receive a reset. Asserts on the second window timeout.

Active-High:
SWDT_RST_PEND

IRQ
I/O

Generic window 0 indicator N/A Generic timer window 0 active.

Active-High:
SWDT_GWS0

IRQ
I/O

Generic window 1 indicator N/A Generic timer window 1 active.

Active-High:
SWDT_GWS1

IRQ
I/O