Slave Send Polled

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English
Table 1. I2C Slave Send Polled
Task Register Register Field Bits Operation
Use RXRW bit in status register to wait master to start a read.
Read status register Status, 0x04 All 8:0 Read operation
Check the RXRW bit is set by reading status register continuously. If master tries to send data, it is an error.
Read interrupt status register ISR, 0x10 All 9:0 Read operation
Write back interrupt status register ISR, 0x10 All 9:0 Clear bits detected as set
Send data as long as there is more data to send and there are no errors (see Send Byte).
Read status register Status, 0x04 All 8:0 Read operation
Wait for master to read the data out of the TX FIFO; [SR] & [TXDV] != 0 and there are no errors.
Read interrupt status register ISR, 0x10 All 9:0 Read operation
If master terminates the transfer before all data is sent, it is an error (interrupt status register and NACK).
Write back interrupt status register ISR, 0x10 All 9:0 Clear bits detected as set